F-Tile Interlaken Intel FPGA IP Design Example

Tataiso ea ho Qala ka Potlako

F-Tile Interlaken Intel® FPGA IP ea mantlha e fana ka benche ea teko ea papali. Moetso oa hardware example e tšehetsang tlhahlobo le tlhahlobo ea hardware e tla fumaneha ho Intel Quartus® Prime Pro Edition software version 21.4. Ha o hlahisa moqapi example, mohlophisi oa parameter o iketsetsa faele ea files bohlokoa ho etsisa, ho bokella, le ho leka moralo.
The testbench le moralo example e ts'ehetsa mokhoa oa NRZ le PAM4 bakeng sa lisebelisoa tsa F-tile. F-Tile Interlaken Intel FPGA IP mantlha e hlahisa moralo oa examples bakeng sa metsoako e latelang e tšehetsoeng ea palo ea litselana le litefiso tsa data.

IP e Tšehetsoeng Metsoako ea Palo ea Lane le Litefiso tsa data
Metsoako e latelang e tšehetsoa ho Intel Quartus Prime Pro Edition software version 21.3. Likopano tse ling kaofela li tla tšehetsoa molemong oa nakong e tlang oa Intel Quartus Prime Pro Edition.

Palo ea Litsela	Rate ea Lane (Gbps)
	6.25	10.3125	12.5	25.78125	53.125
4	Ee	–	Ee	Ee	–
6	–	–	–	Ee	Ee
8	–	–	Ee	Ee	–
10	–	–	Ee	Ee	–
12	–	Ee	Ee	Ee	–

Setšoantšo sa 1.Mehato ea Ntlafatso ea Moqapi Example

Hlokomela: Hardware Compilation and Testing e tla fumaneha ho Intel Quartus Prime Pro Edition software version 21.4.
F-Tile Interlaken Intel FPGA IP core design example e tšehetsa likarolo tse latelang:

• Ka hare TX ho RX serial loopback mode
• E iketsetsa lipakete tsa boholo bo tsitsitseng
• Bokhoni ba ho hlahloba pakete ea mantlha
• Bokhoni ba ho sebelisa System Console ho hlophisa moralo bocha molemong oa ho etsa liteko hape

Setšoantšo sa 2. Setšoantšo sa Block Block se phahameng

Lintlha Tse Amanang

• F-Tile Interlaken Intel FPGA IP User Guide
• Lintlha tsa Phallo ea F-Tile Interlaken Intel FPGA IP

Litlhoko tsa Hardware le Software

Ho leka example design, sebelisa hardware le software tse latelang:

• Intel Quartus Prime Pro Edition software version 21.3
• Console ea tsamaiso
• Simulator e tšehelitsoeng:
  • Synopsy* VCS*
  • Litlhaloso tsa VCS MX
  • Siemens* EDA ModelSim* SE kapa Questa*

Hlokomela:  Tšehetso ea lisebelisoa bakeng sa moqapi oa exampe tla fumaneha ho Intel Quartus Prime Pro Edition software version 21.4.

Ho Hlahisa Moralo

Setšoantšo sa 3. Tsamaiso

Latela mehato ena ho hlahisa ex designample le testbench:

1. Ho software ea Intel Quartus Prime Pro Edition, tobetsa File ➤ Project Wizard e Ncha ho theha projeke e ncha ea Intel Quartus Prime, kapa tobetsa File ➤ Open Project ho bula morero o teng oa Intel Quartus Prime. Wizate e o kopa hore o hlalose sesebediswa.
2. Hlalosa lelapa la sesebelisoa sa Agilex ebe u khetha sesebelisoa se nang le F-Tile bakeng sa moralo oa hau.
3. Ho IP Catalog, fumana le ho penya habeli F-Tile Interlaken Intel FPGA IP. Ho hlaha fensetere e ncha ea IP Variant.
4. Hlalosa lebitso la boemo bo holimo bakeng sa phapang ea hau ea IP e tloaelehileng. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file bitsetsoe .ip.
5. Tobetsa OK. Mohlophisi oa parameter oa hlaha.

Setšoantšo sa 4. Example Design Tab

6. Ho tab ya IP, hlakisa maemo bakeng sa phapano ya mantlha ya IP ya hao.
7. Ho Example Design tab, khetha khetho ea Simulation ho hlahisa testbench.
Tlhokomeliso: Khetho ea Synthesis ke ea hardware example design, e tla fumaneha ho Intel Quartus Prime Pro Edition software version 21.4.
8. Bakeng sa Hlahisa HDL Format, ka bobeli Verilog le VHDL kgetho e teng.
9. Tobetsa Hlahisa Example Design. The Khetha Exampho hlaha fensetere ea Design Directory.
10. Haeba u batla ho fetola moralo examptsela ea directory kapa lebitso ho tsoa ho li-defaults tse bontšitsoeng (ilk_f_0_example_design), sheba tsela e ncha ebe u thaepa sebopeho se secha sa example lebitso la directory.
11. Tlanya OK.

Hlokomela: Ka sebopeho sa F-Tile Interlaken Intel FPGA IP example, SystemPLL e kenngoa ka bo eona, 'me e hokahane le F-Tile Interlaken Intel FPGA IP core. The SystemPLL hierarchy path in the design example ke:

example_design.test_env_inst.test_dut.dut.pll

The SystemPLL ka moralo example e arolelana oache e tšoanang ea 156.26 MHz joalo ka Transceiver.

Sebopeho sa Directory

F-Tile Interlaken Intel FPGA IP ea mantlha e hlahisa tse latelang files bakeng sa moralo exampLe:
Setšoantšo sa 5. Sebopeho sa Directory

Lethathamo la 2. Moqapi oa lisebelisoa tsa thepa Example File Litlhaloso
Tsena files li hoample_installation_dir>/ilk_f_0_example_design directory.

File Mabitso	Tlhaloso
example_design.qpf	Morero oa mantlha oa Intel Quartus file.
example_design.qsf	Litlhophiso tsa projeke ea Intel Quartus Prime file
example_design.sdc jtag_timing_template.sdc	Synopsys Design Constraint file. U ka kopitsa le ho fetola moralo oa hau.
sysconsole_testbench.tcl	Ka sehloohong file bakeng sa ho fihlella System Console

Hlokomela: Tšehetso ea lisebelisoa bakeng sa moqapi oa exampe tla fumaneha ho Intel Quartus Prime Pro Edition software version 21.4.

Letlapa la 3. Testbench File Tlhaloso

Sena file e ka har'aample_installation_dir>/ilk_f_0_example_design/ mohlalaample_design/rtl directory.

File Lebitso	Tlhaloso
top_tb.sv	Testbench ea boemo bo holimo file.

Letlapa la 4. Litemana tsa Testbench

Tsena files li hoample_installation_dir>/ilk_f_0_example_design/ mohlalaample_design/testbench directory

File Lebitso	Tlhaloso
run_vcs.sh	Mongolo oa Synopsys VCS ho tsamaisa testbench.
run_vcsmx.sh	Sengoloa sa Synopsys VCS MX ho tsamaisa testbench.
run_mentor.tcl	The Siemens EDA ModelSim SE kapa Questa script ho tsamaisa testbench.

Ho Etsisa Moralo Example Testbench

Setšoantšo sa 6. Mokhoa

Latela mehato ena ho etsisa testbench:

1. Ka potlako ea taelo, fetola ho directory ea simulation ea testbench. Tsela ea directory keample_installation_dir>/example_design/ testbench.
2. Matha sengoloa sa ketsiso bakeng sa simulator e tšehelitsoeng eo u e khethileng. Script e bokella le ho tsamaisa testbench ho simulator. Sengoliloeng sa hau se lokela ho lekola hore SOP le EOP li bapana ka mor'a hore papiso e felile.

Lethathamo la 5. Mehato ea ho Matha Ketsiso

Moetsisi	Litaelo
VCS	Moleng oa taelo, thaepa:   sh run_vcs.sh
Tlhaloso: VCS MX	Moleng oa taelo, thaepa:   sh run_vcsmx.sh
ModelSim SE kapa Questa	Moleng oa taelo, thaepa:   vsim -do run_mentor.tcl Haeba u khetha ho etsisa ntle le ho hlahisa ModelSim GUI, thaepa:   vsim -c -etsa run_mentor.tcl

3. Sekaseka liphello. Ketsiso e atlehileng e romella le ho amohela lipakete, 'me e bonts'a "Test PASSED".

The testbench bakeng sa moralo example phetha mesebetsi e latelang:

• E tiisa motheo oa F-Tile Interlaken Intel FPGA IP.
• E hatisa boemo ba PHY.
• E hlahloba khokahano ea metaframe (SYNC_LOCK) le meeli ea lentsoe (thibelo) (WORD_LOCK).
• E emetse hore litselana ka bomong li notleloe le ho lokisoa.
• E qala ho tsamaisa lipakete.
• E hlahloba lipalo-palo tsa liphutheloana:
  • CRC24 liphoso
  • SOPs
  • EOPs

Tse latelang sample output e bonts'a ts'ebetso e atlehileng ea teko ea ketsiso:

Ho Kopanya Moralo Example

1. Netefatsa hore example tlhahiso ea moralo e felile.
2. Ho software ea Intel Quartus Prime Pro Edition, bula morero oa Intel Quartus Primeample_installation_dir>/example_design.qpf>.
3. Ho menu ea Processing, tobetsa Start Compilation.

Moqapi Example Tlhaloso

Moqapi example e bonts'a ts'ebetso ea mantlha ea IP ea Interlaken.

Moqapi Example Likarolo

Example design e hokahanya lioache tsa litšupiso tsa sistimi le PLL le likarolo tse hlokahalang tsa moralo. Example design e hlophisa mantlha ea IP ka har'a mokhoa oa ka hare oa loopback mme e hlahisa lipakete ho sebopeho sa phetiso ea data ea mosebelisi ea IP core TX. IP core e romela lipakete tsena tseleng e ka hare ea loopback ka transceiver.
Kamora hore moamoheli oa mantlha oa IP a fumane lipakete tseleng ea loopback, e sebetsana le lipakete tsa Interlaken ebe e li fetisetsa ho sebopeho sa phetisetso ea data ea RX. Example design e lekola hore na lipakete li amohetse le ho fetisoa li ts'oana.
Moralo oa F-Tile Interlaken Intel IP example kenyeletsa likarolo tse latelang:

1. F-Tile Interlaken Intel FPGA IP ea mantlha
2. Pakete jenereithara le Pakete Checker
3. Reference F-Tile le System PLL Clocks Intel FPGA IP core

Lipontšo tsa Interface

Lethathamo la 6. Moqapi Example Lipontšo tsa Interface

Lebitso la Port	Tataiso	Bophara (Bits)	Tlhaloso
mgmt_clk	Kenyeletso	1	Ho kenya oache ea sistimi. Maqhubu a oache a tlameha ho ba 100 MHz.
pll_ref_clk	Kenyeletso	1	Oache ea litšupiso ea transceiver. E tsamaisa RX CDR PLL.
rx_pin	Kenyeletso	Palo ea litselana	Receiver SERDES phini ea data.
tx_pin	Sephetho	Palo ea litselana	Fetisetsa PIN ea data ea SERDES.
rx_pin_n(1)	Kenyeletso	Palo ea litselana	Receiver SERDES phini ea data.
tx_pin_n(1)	Sephetho	Palo ea litselana	Fetisetsa PIN ea data ea SERDES.
mac_clk_pll_ref	Kenyeletso	1	Letšoao lena le tlameha ho tsamaisoa ke PLL 'me le tlameha ho sebelisa mohloli o tšoanang oa oache o tsamaisang pll_ref_clk. Letšoao lena le fumaneha feela ka mefuta ea lisebelisoa tsa PAM4.
usr_pb_reset_n	Kenyeletso	1	Sesebelisoa sa reset.

(1) E fumaneha feela ka mefuta ea PAM4.

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.
*Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

Ngolisa 'mapa

Hlokomela:

• Moqapi ExampAterese ea register e qala ka 0x20** ha aterese ea mantlha ea IP ea Interlaken e qala ka 0x10**.
• Aterese ea ngoliso ea F-tile PHY e qala ka 0x30** ha aterese ea F-tile FEC e qala ka 0x40**. Ngoliso ea FEC e fumaneha feela ka mokhoa oa PAM4.
• Khouto ea ho kena: RO—Bala Feela, le RW—Bala/Ngola.
• System console e bala sebopeho sa exampe ngolisa le ho tlaleha boemo ba teko skrineng.

Lethathamo la 7. Moqapi Example Register Map

Offset	Lebitso	Phihlello	Tlhaloso
8h00	Reserved
8h01	Reserved
8h02	Sistimi ea PLL e nchafalitsoe	RO	Li-bits tse latelang li bonts'a kopo ea ho seta bocha PLL le ho nolofalletsa boleng: • Bit [0] – sys_pll_rst_req • Bit [1] – sys_pll_rst_en
8h03	RX lane e tsamaellana	RO	E bonts'a tlhophiso ea tsela ea RX.
8h04	LENTSOE notletsoe	RO	[NUM_LANES–1:0] – Tlhaloso ea meeli ea Lentsoe (thibelo).
8h05	Khokahano e notletsoe	RO	[NUM_LANES–1:0] – Khokahano ea Metaframe.
8'h06 - 8'h09	CRC32 palo ea liphoso	RO	E bontša palo ea liphoso tsa CRC32.
8h0A	CRC24 palo ea liphoso	RO	E bontša palo ea liphoso tsa CRC24.
8h0b	Lets'oao la ho phalla / Tlaaseha	RO	Lintlha tse latelang li bontša: • Bit [3] - TX lets'oao la phallo e tlase • Bit [2] - Letšoao la ho phalla la TX • Bit [1] - Letšoao la ho phalla la RX
8h0C	palo ea SOP	RO	E bontša palo ea SOP.
8'h0D	palo ea EOP	RO	E bontša palo ea EOP
8h0E	Palo ea liphoso	RO	E bontša palo ea liphoso tse latelang: • Ho lahleheloa ke tsela ea tsela • Lentsoe la taolo e seng molaong • Paterone e seng molaong ea ho etsa liforeimi • SOP kapa EOP sesupa se sieo
8'h0F	send_data_mm_clk	RW	Ngola 1 ho bit [0] ho nolofalletsa lets'oao la jenereithara.
8h10	Phoso ea ho hlahloba		E bontša phoso ea ho hlahloba. (Phoso ea data ea SOP, phoso ea nomoro ea Channel, le phoso ea data ea PLD)
8h11	Sistimi PLL senotlolo	RO	Bit [0] e supa sesupo sa senotlolo sa PLL.
8h14	TX SOP palo	RO	E bontša palo ea SOP e hlahisoang ke jenereithara ea pakete.
8h15	TX EOP palo	RO	E bontša palo ea EOP e hlahisoang ke jenereithara ea pakete.
8h16	Phakete e tsoelang pele	RW	Ngola ho tloha ho 1 ho isa ho [0] ho nolofalletsa pakete e tsoelang pele.
e tsoela pele…

Offset	Lebitso	Phihlello	Tlhaloso
8h39	ECC palo ea liphoso	RO	E bontša palo ea liphoso tsa ECC.
8h40	ECC e lokisitse palo ea liphoso	RO	E bontša palo ea liphoso tse lokisitsoeng tsa ECC.
8h50	tile_tx_rst_n	WO	Khutlisetsa thaele ho SRC bakeng sa TX.
8h51	tile_rx_rst_n	WO	Khutlisetsa thaele ho SRC bakeng sa RX.
8h52	tile_tx_rst_ack_n	RO	Tumellano ea ho tsosolosa thaele ho tsoa ho SRC bakeng sa TX.
8h53	tile_rx_rst_ack_n	RO	Ho seta botjha ha thaele ho dumela ho tswa ho SRC bakeng sa RX.

Seta bocha

Ho F-Tile Interlaken Intel FPGA IP mantlha, o qala ho reset (reset_n=0) ebe o ts'oara ho fihlela IP core e khutlisa tumello ea ho seta bocha (reset_ack_n=0). Ka mor'a hore reset e tlosoe (reset_n=1), tumello ea ho tsosolosa e khutlela boemong ba eona ba pele.
(reset_ack_n=1). Ka moralo exampLeha ho le joalo, rst_ack_sticky registeri e boloka polelo ea tumello ea ho seta hape ebe e etsa hore ho tlosoe reset (reset_n=1). U ka sebelisa mekhoa e meng e lumellanang le litlhoko tsa hau tsa moralo.

Bohlokoa: Boemong bofe kapa bofe moo serial loopback e hlokahalang, o tlameha ho lokolla TX le RX tsa F-tile ka thoko ka tatellano e itseng. Sheba sengoloa sa console sa sistimi bakeng sa tlhaiso-leseling e batsi.

Setšoantšo sa 7. Khutlisa Tatelano ho Mokhoa oa NRZ

Setšoantšo sa 8.Reset Sequence ho PAM4 Mode

F-Tile Interlaken Intel FPGA IP Design Example User Guide Archives

Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.

Intel Quartus Prime Version	IP Core Version	Bukana ea Mosebelisi
21.2	2.0.0	F-Tile Interlaken Intel FPGA IP Design Example Bukana ea Mosebelisi

Nalane ea Phetoho ea Litokomane bakeng sa F-Tile Interlaken Intel FPGA IP Design Example Bukana ea Mosebelisi

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
2021.10.04	21.3	3.0.0	• Tšehetso e ekelitsoeng bakeng sa metsoako e mecha ea sekhahla sa litselana. Ho fumana lintlha tse ling, sheba ho Lethathamo: Likopano tse Tšehetsoeng ke IP tsa Palo ea Litsela le Sekhahla sa Data. • E ntlafalitse lenane la litšoantšiso tse tšehetsoeng karolong: Litlhoko tsa Hardware le Software. • E kentse lirekoto tse ncha karolong: Ngolisa 'mapa.
2021.06.21	21.2	2.0.0	Tokollo ea pele.

Litokomane / Lisebelisoa

Intel F-Tile Interlaken Intel FPGA IP Design Example [pdf] Bukana ea Mosebelisi F-Tile Interlaken Intel FPGA IP Design Example, F-Tile, Interlaken Intel FPGA IP Design Example, Intel FPGA IP Design Example, IP Design Example, Moqapi Example

Litšupiso

• Bukana ea Mosebelisi