Intel® FPGA P-Tile Avalon ®
Ho phallela IP bakeng sa PCI Express*
Moqapi Example Bukana ea Mosebelisi
E ntlafalitsoe bakeng sa Intel®
Quartus® Prime Design Suite: 21.3
Phetolelo ea IP: 6.0.0
Bukana ea Mosebelisi
Moqapi Example Tlhaloso
1.1. Tlhaloso ea Ts'ebetso bakeng sa Morero o hlophisitsoeng oa Input/Output (PIO) Example
Moqapi oa PIO exampe etsa phetiso ea memori ho tloha ho processor ea moamoheli ho ea ho sesebelisoa se shebiloeng. Ho sena mohlalaample, processor ea moamoheli e kopa single-dword MemRd le emWr
TLPs.
Moqapi oa PIO example ka tsela e iketsang bopa the fileHoa hlokahala ho etsisa le ho bokella software ea Intel Prime. Moqapi exampLe e akaretsa mefuta e mengata ea liparamente. Leha ho le joalo, ha e koahele likarolo tsohle tse ka khonehang tsa P-Tile Hard IP bakeng sa PCIe.
Moqapi ona example kenyeletsa likarolo tse latelang:
- Mofuta o entsoeng oa P-Tile Avalon Streaming Hard IP Endpoint (DUT) o nang le liparamente tseo u li boletseng. Karolo ena e tsamaisa data ea TLP e amohetsoeng ts'ebelisong ea PIO
- Karolo ea PIO Application (APPS), e etsang phetolelo e hlokahalang lipakeng tsa PCI Express TLPs le Avalon-MM e bonolo e ngola le ho bala mohopolong oa onchip.
- Karolo ea on-chip memory (MEM). Bakeng sa 1 × 16 moralo oa example, memori ea on-chip e na le boloko bo le bong ba 16 KB. Bakeng sa 2×8 moralo example, memori ea on-chip e na le li-blocks tse peli tsa 16 KB.
- Reset Release IP: IP ena e na le potoloho ea taolo e nchafalitsoeng ho fihlela sesebelisoa se kene ka botlalo mokhoeng oa mosebelisi. FPGA e fana ka tlhahiso ea INIT_DONE ho bontša hore sesebelisoa se maemong a mosebelisi. IP ea Tokollo Botjha e hlahisa mofuta o fetotsweng wa leqhubu la ka hare la INIT_DONE ho etsa tlhahiso ya nINIT_DONE eo o ka e sebedisang moralong wa hao. Letshwao la nINIT_DONE le phahame ho fihlela sesebediswa kaofela se kena mokgweng wa mosebedisi. Ka mor'a lipolelo tsa nINIT_DONE (tlase), logic eohle e boemong ba mosebedisi 'me e sebetsa ka mokhoa o tloaelehileng. U ka sebelisa lets'oao la nINIT_DONE ka e 'ngoe ea litsela tse latelang:
- Ho kenya ts'ebetso ea kantle kapa ea kahare.
- Ho kenya ts'ebetso ea ho seta bocha ho transceiver le I/O PLLs.
- Ho kenya ts'ebetso ea ho ngola ea li-block tsa meralo joalo ka li-memory blocks tse kentsoeng, mochini oa mmuso le li-registers.
- Ho khanna ka mokhoa o ts'oanang reseta likou tsa ho kenya botjha moralong oa hau.
The simulation testbench instatias PIO moralo example Root Port BFM ho hokahana le sepheo sa Endpoint.
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
ISO 9001:2015 E Ngolisitsoe
Setšoantšo sa 1. Thibela Setšoantšo sa Moqapi oa Platform PIO 1 × 16 Design Example Simulation Testbench
Setšoantšo sa 2. Thibela Setšoantšo sa Moqapi oa Platform PIO 2 × 8 Design Example Simulation Testbench
Lenaneo la teko le ngolla le ho bala lintlha tse tsoang sebakeng se le seng ho memori ea on-chip. E bapisa data e baloang le sephetho se lebelletsoeng. Teko e tlaleha, "Ketsiso e emisitse ka lebaka la ho phethoa ka katleho" haeba ho se liphoso tse hlahang. P-Tile Avalon
Moralo oa ho phallela example e ts'ehetsa litlhophiso tse latelang:
- Gen4 x16 Qetello
- Gen3 x16 Qetello
- Gen4 x8x8 Ntlha ea ho qetela
- Gen3 x8x8 Ntlha ea ho qetela
Hlokomela: The ketsiso testbench bakeng sa PCIe x8x8 PIO moralo example e etselitsoe sehokelo se le seng sa PCIe x8 leha moralo oa 'nete o sebelisa lihokelo tse peli tsa PCIe x8.
Hlokomela: Moqapi ona example e ts'ehetsa feela litlhophiso tsa kamehla ho Parameter Editor ea P-tile Avalon Streaming IP bakeng sa PCI Express.
Setšoantšo sa 3. Likahare tsa Sisteme ea Moqapi oa Platform bakeng sa Phallo ea P-Tile Avalon PCI Express 1×16 PIO Design Example
Moqapi oa Platform o hlahisa moralo ona oa mefuta e fihlang ho Gen4 x16.
Setšoantšo sa 4. Likahare tsa Sisteme ea Moqapi oa Platform bakeng sa Phallo ea P-Tile Avalon PCI Express 2×8 PIO Design Example
Moqapi oa Platform o hlahisa moralo ona oa mefuta e fihlang ho Gen4 x8x8.
1.2. Tlhaloso ea Ts'ebetso ea Motso o le Mong oa I/O Virtualization (SR-IOV) Moqapi Example
Moqapi oa SR-IOV exampe etsa phetiso ea memori ho tloha ho processor ea moamoheli ho ea ho sesebelisoa se shebiloeng. E ts'ehetsa ho fihla ho li-PF tse peli le li-VF tse 32 ka PF.
Moqapi oa SR-IOV example ka tsela e iketsang bopa the fileHoa hlokahala ho etsisa le ho bokella software ea Intel Quartus Prime. U ka khoasolla moralo o hlophisitsoeng ho
Intel Stratix® 10 DX Development Kit kapa Intel Agilex™ Development Kit.
Moqapi ona example kenyeletsa likarolo tse latelang:
- Mofuta o hlahisitsweng wa P-Tile Avalon Streaming (Avalon-ST) IP Endpoint (DUT) o nang le diparamente tseo o di boletseng. Karolo ena e tsamaisa data e amohetsoeng ea TLP ho ts'ebeliso ea SR-IOV.
- Karolo ea SR-IOV Application (APPS), e etsang phetolelo e hlokahalang pakeng tsa PCI Express TLPs le Avalon-ST e bonolo e ngola le ho bala mohopolong oa on-chip. Bakeng sa karolo ea SR-IOV APPS, TLP e baloang ka memori e tla hlahisa Tlatsetso ka data.
- Bakeng sa SR-IOV moralo example tse nang le li-PF tse peli le li-VF tse 32 ka PF, ho na le libaka tsa memori tse 66 tseo moralo o kileng oa li etsaample ka fihlella. Li-PF tse peli li ka fihlella libaka tse peli tsa memori, ha li-VF tse 64 (2 x 32) li ka fihlella libaka tsa memori tsa 64.
- IP ea ho Lokolla bocha.
The ketsiso testbench instatiates SR-IOV moralo example Root Port BFM ho hokahana le sepheo sa Endpoint.
Setšoantšo sa 5. Thibela Setšoantšo sa Moqapi oa Platform SR-IOV 1×16 Design Example Simulation Testbench
Setšoantšo sa 6. Thibela Setšoantšo sa Moqapi oa Platform SR-IOV 2×8 Design Example Simulation Testbench
Lenaneo la liteko le ngolla le ho bala datha ho tsoa sebakeng se le seng mohopolong oa on-chip ho pholletsa le 2 PFs le 32 VFs ka PF. E bapisa data e baloang le e lebelletsoeng
sephetho. Teko e tlaleha, "Ketsiso e emisitse ka lebaka la ho phethoa ka katleho" haeba ho se liphoso tse hlahang.
Moqapi oa SR-IOV example e ts'ehetsa litlhophiso tse latelang:
- Gen4 x16 Qetello
- Gen3 x16 Qetello
- Gen4 x8x8 Ntlha ea ho qetela
- Gen3 x8x8 Ntlha ea ho qetela
Setšoantšo sa 7. Likahare tsa Tsamaiso ea Moqapi oa Platform bakeng sa P-Tile Avalon-ST e nang le SR-IOV bakeng sa PCI Express 1×16 Design Ex.ample
Setšoantšo sa 8. Likahare tsa Tsamaiso ea Moqapi oa Platform bakeng sa P-Tile Avalon-ST e nang le SR-IOV bakeng sa PCI Express 2×8 Design Ex.ample
Tataiso ea ho Qala ka Potlako
U sebelisa software ea Intel Quartus Prime, u ka hlahisa moralo o hlophisitsoeng oa I/O (PIO) example bakeng sa Intel FPGA P-Tile Avalon-ST Hard IP bakeng sa PCI Express* IP core. Moetso o entsoeng exampe bonts'a liparamente tseo u li boletseng. Mohlala oa PIOampe fetisetsa data ho tsoa ho processor ea moamoheli ho ea ho sesebelisoa se shebiloeng. E loketse lits'ebetso tse tlase tsa bandwidth. Moqapi ona example ka tsela e iketsang bopa the fileHoa hlokahala ho etsisa le ho bokella software ea Intel Quartus Prime. U ka khoasolla moralo o hlophisitsoeng ho FPGA Development Board ea hau. Ho khoasolla ho hardware ea tloaelo, nchafatsa Intel Quartus Prime Settings File (.qsf) ka likabelo tse nepahetseng tsa phini . Setšoantšo sa 9. Mehato ea Ntlafatso ea Moqapi Example
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
ISO 9001:2015 E Ngolisitsoe
2.1. Sebopeho sa Directory
Setšoantšo sa 10. Sebopeho sa Directory bakeng sa Moqapi o Hlatsoeng Example
2.2. Ho Hlahisa Moqapi Example
Setšoantšo sa 11. Mokhoa
- Ho software ea Intel Quartus Prime Pro Edition, theha morero o mocha (File ➤ Setsebi se Secha sa Morero).
- Hlalosa Directory, Lebitso, le Setsi sa Boemo ba Holimo.
- Bakeng sa Mofuta oa Morero, amohela boleng ba kamehla, morero o se nang letho. Tobetsa E latelang.
- Bakeng sa Add Files tobetsa E 'ngoe.
- Bakeng sa Litlhophiso tsa Lelapa, Sesebelisoa le Boto tlas'a Lelapa, khetha Intel Agilex kapa Intel Stratix 10.
- Haeba u khethile Intel Stratix 10 mohatong oa ho qetela, khetha Stratix 10 DX ho menu ea ho theola sesebelisoa.
- Khetha Sesebelisoa sa Target bakeng sa moralo oa hau.
- Tobetsa Qetella.
- Ho IP Catalog fumana 'me u kenye Intel P-Tile Avalon-ST Hard IP bakeng sa PCI Express.
- Ka har'a lebokose la puisano la New IP Variant, bolela lebitso la IP ea hau. Tobetsa Create.
- Ho li-tab tsa Litlhophiso tsa Boemo bo Phahameng le PCIe *, hlakisa li-parameter bakeng sa phapano ea hau ea IP. Haeba u sebelisa moralo oa SR-IOV example, etsa mehato e latelang ho thusa SR-IOV:
a. Ho tab ea PCIe * Sesebelisoa tlas'a tab ea PCIe * PCI Express / PCI, hlahloba lebokose Numella mesebetsi e mengata ea 'mele.
b. Ho PCIe * Multifunction le SR-IOV System Settings tab ya, sheba lebokose Numella tšehetso ea SR-IOV 'me u hlalose palo ea li-PF le VF. Bakeng sa litlhophiso tsa x8, hlahloba mabokose Numella mesebetsi e mengata ea 'mele 'me u Nolofatse tšehetso ea SR-IOV bakeng sa li-tab tsa PCIe0 le PCIe1 ka bobeli.
c. Ho PCIe * MSI-X tab e tlas'a PCIe * PCI Express / PCI Capabilities tab, nolofalletsa karolo ea MSI-X kamoo ho hlokahalang.
d. Ho "PCIe * Base Address Registers" tab, nolofalletsa BAR0 bakeng sa PF le VF ka bobeli.
e. Litlhophiso tse ling tsa paramethara ha li sebetse molemong oa mohlala onaample. - Ho Example Designs tab, etsa likhetho tse latelang:
a. Bakeng sa Example Design Files, bulela khetho ea Simulation le Synthesis.
Haeba u sa hloke ketsiso ena kapa synthesis files, ho siea khetho(s) e tsamaellanang ho tima ho fokotsa haholo example moralo oa tlhahiso ea nako.
b. Bakeng sa Format e Hlahisitsoeng ea HDL, ke Verilog feela e fumanehang tokollong ea hajoale.
c. Bakeng sa Target Development Kit, khetha Intel Stratix 10 DX P-Tile ES1 FPGA Development Kit, Intel Stratix 10 DX P-Tile Production FPGA Development Kit kapa Intel Agilex F-Series P-Tile ES0 FPGA Development Kit.
13. Kgetha Hlahisa Example Moralo oa ho theha mohlala oa moraloample hore o ka etsisa le ho jarolla ho hardware. Haeba u khetha e 'ngoe ea liboto tsa nts'etsopele ea P-Tile, sesebelisoa se botong seo se hlakola sesebelisoa se neng se khethiloe pele ho projeke ea Intel Quartus Prime haeba lisebelisoa li fapane. Ha molaetsa o o kopa hore o hlalose directory bakeng sa ex ea hauample design, o ka amohela lethathamo la kamehla, ./intel_pcie_ptile_ast_0_example_design, kapa khetha bukana e 'ngoe.
Setšoantšo sa 12. Example Designs Tab
- Tobetsa Qetella. U ka boloka .ip ea hau file ha o khothalletsoa, empa ha ho hlokahale hore o khone ho sebelisa exampmoralo.
- Bula example morero oa moralo.
- Kopanya example moralo oa morero oa ho hlahisa .sof file bakeng sa ex e feletsengample moralo. Sena file ke seo u se jarollang ho boto ho etsa netefatso ea lisebelisoa.
- Koala ex ea hauample morero oa moralo.
Hlokomela hore u ke ke ua fetola likabelo tsa phini tsa PCIe morerong oa Intel Quartus Prime. Leha ho le joalo, ho nolofatsa mokhoa oa PCB, o ka nka advantage ea likarolo tsa phetoho ea lane le polarity inversion e tšehetsoeng ke IP ena.
2.3. Ho etsisa Moqapi Example
Mokhoa oa ho etsisa o kenyelletsa tšebeliso ea Root Port Bus Functional Model (BFM) ho sebelisa P-tile Avalon Streaming IP bakeng sa PCIe (DUT) joalokaha ho bontšitsoe ho tse latelang.
setšoantšo.
Setšoantšo sa 13. PIO Design Example Simulation Testbench
Bakeng sa lintlha tse ling mabapi le testbench le li-module tse ho eona, sheba Testbench leqepheng la 15.
Setšoantšo se latelang sa phallo se bontša mehato ea ho etsisa moqapi oa exampLe:
Setšoantšo sa 14. Tsamaiso
- Fetolela bukeng ea simulation ea testbench, / pcie_ed_tb/pcie_ed_tb/sim/ /setsisi.
- Matha sengoloa sa ketsiso bakeng sa simulator ea khetho ea hau. Sheba tafole e ka tlase.
- Sekaseka liphello.
Hlokomela: P-Tile ha e tšehetse lipapiso tse tšoanang tsa PIPE.
Lethathamo la 1. Mehato ea ho Matha Ketsiso
| Moetsisi | Bukana ea Mosebetsi | Litaelo |
| ModelSim* SE, Siemens* EDA QuestaSim*- Intel FPGA Edition | <example_design>/pcie_ed_tb/ pcie_ed_tb/sim/mentor/ | 1. Kopa vsim (ka ho thaepa vsim, e hlahisang fensetere ea console moo o ka tsamaisang litaelo tse latelang). 2. etsa msim_setup.tcl Ela hloko: Ho seng joalo, sebakeng sa ho etsa Mehato ea 1 le ea 2, o ka ngola: vsim -c -do msim_setup.tcl. 3. ld_debug 4. matha -ohle 5. Papiso e atlehileng e qetella ka molaetsa o latelang, "Ketsiso e emisitse ka lebaka la ho phethoa ka katleho!" |
| VCS* | <example_design>/pcie_ed_tb/ pcie_ed_tb/sim/synopsy/vcs | 1. Tlanya sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS=””USER_DEFINED_ELAB_OPTIONS=”-xlrm\ uniq_prior_final” USER_DEFINED_SIM_OPTIONS=” |
| e tsoela pele… | ||
| Moetsisi | Bukana ea Mosebetsi | Litaelo |
| Tlhokomeliso: Taelo e ka holimo ke taelo ea mola o le mong. 2. Papiso e atlehileng e qetella ka molaetsa o latelang, "Ketsiso e emisitse ka lebaka la ho phethoa ka katleho!" Tlhokomeliso: Ho etsa papiso ka mokhoa oa ho sebelisana, sebelisa mehato e latelang: (haeba u se u hlahisitse simv e ka phethisoang ka mokhoa o sa sebeliseng, hlakola simv le simv.diadir) 1. Bula faele ea vcs_setup.sh file 'me u kenye khetho ea debug ho taelo ea VCS: vcs -debug_access+r 2. Kopanya mohlala oa moraloample: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS=”- xlrm\ uniq_prior_final” SKIP_SIM=1 3. Qala ketsiso ka mokhoa oa ho sebelisana: simv -gui & |
Testbench ena e etsisa mofuta oa Gen4 x16.
Ketsiso e tlaleha, "Ketsiso e emisitse ka lebaka la ho phetheloa ka katleho" haeba ho se na liphoso tse etsahalang.
2.3.1. Testbench
Testbench e sebelisa mochine oa mokhanni oa teko, altpcietb_bfm_rp_gen4_x16.sv, ho qala ts'ebetso ea tlhophiso le memori. Ha u qala, mochine oa mokhanni oa teko o bonts'a tlhahisoleseding e tsoang ho Root Port le Endpoint Configuration Space registers, e le hore u ka ikamahanya le litekanyo tseo u li boletseng u sebelisa Parameter Editor.
Example design le testbench li hlahisoa ka matla ho latela tlhophiso eo u e khethang bakeng sa P-Tile IP bakeng sa PCIe. Testbench e sebelisa li-parameter tseo u li hlalosang ho Parameter Editor ho Intel Quartus Prime. Testbench ena e etsisa sehokelo sa × 16 PCI Express e sebelisa sebopeho sa serial PCI Express. Moralo oa testbench o lumella lihokelo tse fetang tse le 'ngoe tsa PCI Express hore li etsisoe ka nako. Setšoantšo se latelang se hlahisa boemo bo phahameng view ea moralo oa PIO example.
Setšoantšo sa 15. PIO Design Example Simulation Testbench
Boemo bo holimo ba testbench bo tiisa li-module tse latelang tse kholo:
- altpcietb_bfm_rp_gen4x16.sv —Ena ke Root Port PCIe BFM.
// Tsela ea bukana
/intel_pcie_ptile_ast_0_example_design/pcie_ed_tb/ip/
pcie_ed_tb/dut_pcie_tb_ip/intel_pcie_ptile_tbed_ /sim - pcie_ed_dut.ip: Ona ke moralo oa Endpoint o nang le li-parameter tseo u li hlalosang.
// Tsela ea bukana
/intel_pcie_ptile_ast_0_example_design/ip/pcie_ed - pcie_ed_pio0.ip: Mojule ona ke sepheo le mothehi oa litšebelisano bakeng sa moralo oa PIO ex.ample.
// Tsela ea bukana
/intel_pcie_ptile_ast_0_example_design/ip/pcie_ed - pcie_ed_sriov0.ip: Mojule ona ke sepheo le mothehi oa litšebelisano bakeng sa SR-IOV design ex.ample.
// Tsela ea bukana
/intel_pcie_ptile_ast_0_example_design/ip/pcie_ed
Setšoantšo sa 16. SR-IOV Design Example Simulation Testbench
Ntle le moo, testbench e na le litloaelo tse etsang mesebetsi e latelang:
- E hlahisa oache ea litšupiso bakeng sa Endpoint ka makhetlo a hlokahalang.
- E fana ka PCI Express reset qalong.
Bakeng sa lintlha tse ling mabapi le Root Port BFM, sheba khaolo ea TestBench ea Intel FPGA P-Tile Avalon e phallelang IP bakeng sa Tataiso ea Mosebelisi ea PCI Express.
Lintlha Tse Amanang
Intel FPGA P-Tile Avalon e phallela IP bakeng sa Tataiso ea Mosebelisi ea PCI Express
2.3.1.1. Test Driver Module
Mojule oa mokhanni oa teko, intel_pcie_ptile_tbed_hwtcl.v, o tiisa toplevel BFM,altpcietb_bfm_top_rp.v.
BFM ea boemo bo holimo e phethela mesebetsi e latelang:
- E tiisa mokhanni le ho beha leihlo.
- E tiisa Root Port BFM.
- E tiisa sebopeho sa serial.
Mojule oa tlhophiso, altpcietb_g3bfm_configure.v, o etsa mesebetsi e latelang:
- E lokisa le ho abela li-BAR.
- E lokisa Root Port le Endpoint.
- E bontša sebaka se felletseng sa Configuration, BAR, MSI, MSI-X, le li-setting tsa AER.
2.3.1.2. PIO Design Example Testbench
Setšoantšo se ka tlase se bonts'a sebopeho sa PIO example ketsiso moralo hierarchy. Liteko tsa moralo oa PIO example li hlalosoa ka lisebelisoa_type_hwtcl parameter e behiloeng ho
3. Liteko tse etsoang tlas'a boleng ba parameter ena li hlalosoa ho ebfm_cfg_rp_ep_rootport, find_mem_bar le downstream_loop.
Setšoantšo sa 17. PIO Design Example Simulation Design Hierarchy
Testbench e qala ka koetliso ea li-link ebe e fihlella sebaka sa tlhophiso ea IP bakeng sa ho bala. Mosebetsi o bitsoang downstream_loop (e hlalositsoeng ho Root Port
PCIe BFM altpcietb_bfm_rp_gen4_x16.sv) ebe e etsa tlhahlobo ea khokahano ea PCIe. Teko ena e na le mehato e latelang:
- Fana ka taelo ea ho ngola memori ho ngola dword e le 'ngoe ea data mohopolong oa on-chip ka morao ho Endpoint.
- Fana ka taelo ea ho bala memori ho bala data morao ho memori ea on-chip.
- Bapisa data e baloang le data ea ho ngola. Haeba li lumellana, tlhahlobo e nka sena e le Pase.
- Pheta mehato ea 1, ea 2 le ea 3 bakeng sa makhetlo a 10.
Mongolo oa pele oa memori o etsahala ho pota 219 rona. E lateloa ke memori e baloang sebopehong sa Avalon-ST RX sa P-tile Hard IP bakeng sa PCIe. Completion TLP e hlaha nakoana kamora kopo ea ho bala mohopolo ho sebopeho sa Avalon-ST TX.
2.3.1.3. SR-IOV Design Example Testbench
Setšoantšo se ka tlase se bonts'a moralo oa SR-IOV example ketsiso moralo hierarchy. Liteko tsa moralo oa SR-IOV exampli etsoa ke mosebetsi o bitsoang sriov_test,
e hlalosoang ho altpcietb_bfm_cfbp.sv.
Setšoantšo sa 18. SR-IOV Design Example Simulation Design Hierarchy
SR-IOV testbench e tšehetsa ho fihlela ho tse peli tsa Physical Functions (PFs) le 32 Virtual Functions (VFs) ka PF.
Testbench e qala ka koetliso ea li-link ebe e fihlella sebaka sa tlhophiso ea IP bakeng sa ho bala. Ka mor'a moo, e etsa mehato e latelang:
- Romela kopo ea ho ngola memori ho PF e lateloang ke kopo ea ho bala ka memori ho bala data e tšoanang ho bapisa. Haeba data e baloang e lumellana le data e ngotsoeng, ho joalo
Phase. Teko ena e etsoa ke mosebetsi o bitsoang my_test (e hlalosoang ho altpcietb_bfm_cfbp.v). Teko ena e phetoa habeli bakeng sa PF ka 'ngoe. - Romela kopo ea ho ngola memori ho VF e lateloang ke kopo ea ho bala memori ho bala hape data e tšoanang bakeng sa ho bapisa. Haeba data e baloang e lumellana le data e ngotsoeng, ho joalo
Phase. Teko ena e etsoa ke mosebetsi o bitsoang cfbp_target_test (e hlalosoang ho altpcietb_bfm_cfbp.v). Teko ena e phetoa bakeng sa VF ka 'ngoe.
Mongolo oa pele oa memori o etsahala ho pota 263 rona. E lateloa ke memori e baloang sebopehong sa Avalon-ST RX sa PF0 ea P-tile Hard IP bakeng sa PCIe. Completion TLP e hlaha nakoana kamora kopo ea ho bala mohopolo ho sebopeho sa Avalon-ST TX.
2.4. Ho Kopanya Moralo Example
- Tsamaisa ho /intel_pcie_ptile_ast_0_example_design/ mme o bule pcie_ed.qpf.
- Haeba u khetha e 'ngoe ea lisebelisoa tsa ntlafatso tse peli tse latelang, litlhophiso tse amanang le VID li kenyellelitsoe ho .qsf file ea moetso o entsoeng example, 'me ha ho hlokahale hore u li kenye ka letsoho. Hlokomela hore litlhophiso tsena li khethiloe ka boto.
• Intel Stratix 10 DX P-Tile ES1 FPGA kit ea ntlafatso
• Intel Stratix 10 DX P-Tile Production FPGA kit ea ntshetsopele
• Intel Agilex F-Series P-Tile ES0 FPGA kit ea ntlafatso - Ho "Processing" menu, khetha "Start Compilation".
2.5. Ho kenya Linux Kernel Driver
Pele o ka leka sebopeho sa exampka hardware, o tlameha ho kenya Linux kernel
mokhanni. U ka sebelisa mokhanni enoa ho etsa liteko tse latelang:
• Teko ea khokahano ea PCIe e etsang 100 ea ho ngola le ho bala
• Sebaka sa memori DWORD
ho bala le ho ngola
• Sebakeng sa Tlhophiso DWORD e bala le ho ngola
(1)
Ntle le moo, o ka sebelisa mokhanni ho fetola boleng ba liparamente tse latelang:
• BAR e sebelisoang
• Sesebelisoa se khethiloeng (ka ho hlakisa linomoro tsa bese, sesebelisoa le tšebetso (BDF) bakeng sa
sesebelisoa)
Tlatsa mehato e latelang ho kenya kernel driver:
- Tsamaea ho ./software/kernel/linux tlasa example bukana ea tlhahiso ea moralo.
- Fetola tumello ea ho kenya, ho kenya, le ho laolla files:
$ chmod 777 kenya mojaro oa ho theola - Kenya driver:
$ sudo ./install - Netefatsa ho kenya mokhanni:
$ lsmod | grep intel_fpga_pcie_drv
Sephetho se lebelletsoeng:
intel_fpga_pcie_drv 17792 0 - Netefatsa hore Linux e hlokomela sebopeho sa PCIe exampLe:
$ lspci -d 1172:000 -v | grep intel_fpga_pcie_drv
Hlokomela: Haeba u fetotse ID ea Morekisi, kenya ID ea Morekisi e ncha bakeng sa Intel's
ID ea morekisi taelong ena.
Sephetho se lebelletsoeng:
Mokhanni oa Kernel ea sebetsang: intel_fpga_pcie_drv
2.6. Ho tsamaisa Moqapi Example
Mona ke lits'ebetso tsa liteko tseo u ka li etsang ho P-Tile Avalon-ST PCIe design examphanyane:
- Ho pholletsa le tataiso ena ea basebelisi, mantsoe a lentsoe, DWORD le QWORD a na le moelelo o tšoanang le oo a nang le oona ho PCI Express Base Specification. Lentsoe ke likotoana tse 16, DWORD ke likotoana tse 32, 'me QWORD ke likotoana tse 64.
Letlapa la 2. Ts'ebetso ea Teko e Tšehetsoeng ke P-Tile Avalon-ST PCIe Design Examples
| Ts'ebetso | E hlokehang BAR | E tšehetsoa ke P-Tile Avalon-ST PCIe Design Example |
| 0: Teko ea khokahano - 100 e ngola ebile e bala | 0 | Ee |
| 1: Ngola sebaka sa memori | 0 | Ee |
| 2: Bala sebaka sa mohopolo | 0 | Ee |
| 3: Ngola sebaka sa tlhophiso | N/A | Ee |
| 4: Bala sebaka sa tlhophiso | N/A | Ee |
| 5: Fetola BAR | N/A | Ee |
| 6: Fetola sesebelisoa | N/A | Ee |
| 7: Thusa SR-IOV | N/A | Ho joalo (*) |
| 8: Etsa tlhahlobo ea khokahano bakeng sa ts'ebetso e 'ngoe le e' ngoe e lumelletsoeng ea sesebelisoa sa hajoale | N/A | Ho joalo (*) |
| 9: Etsa DMA | N/A | Che |
| 10: Tlohela lenaneo | N/A | Ee |
Tlhokomeliso: (*) Ts'ebetso tsena tsa liteko li fumaneha feela ha moralo oa SR-IOV example khethiloe.
2.6.1. Ho tsamaisa PIO Design Example
- E ea ho ./software/user/example tlas'a moralo example directory.
- Kopanya moralo example kopo:
$ etsa - Etsa tlhahlobo:
$ sudo ./intel_fpga_pcie_link_test
O ka tsamaisa tlhahlobo ea sehokelo sa Intel FPGA IP PCIe ka mokhoa oa matsoho kapa oa othomathiki. Khetha ho tsoa ho:
• Boemong ba othomathiki, sesebelisoa se ikhethela sesebelisoa. Teko e khetha sesebelisoa sa Intel PCIe se nang le BDF e tlase ka ho ts'oana le ID ea Morekisi.
Teko e boetse e khetha BAR e fumanehang ka tlase.
• Ka mokhoa oa matsoho, tlhahlobo e u botsa ka bese, sesebelisoa, le nomoro ea ts'ebetso le BAR.
Bakeng sa Intel Stratix 10 DX kapa Intel Agilex Development Kit, o ka tseba hore na
BDF ka ho thaepa taelo e latelang:
$ lspci -d 1172:
4. Mona ke sample transcripts bakeng sa mekhoa ea othomathike le ea matsoho:
Mokhoa o itirisang:
Mokhoa oa matsoho:
Lintlha Tse Amanang
PCIe Link Inspector Overview
Sebelisa PCIe Link Inspector ho beha leihlo sehokelo ho Physical, Data Link le Transaction Layers.
2.6.2. Ho tsamaisa SR-IOV Design Example
Mona ke mehato ea ho leka SR-IOV moralo exampka hardware:
- Etsa tlhahlobo ea khokahano ea Intel FPGA IP PCIe ka ho sebelisa sudo ./
taelo ea intel_fpga_pcie_link_test ebe u khetha khetho ea 1:
Khetha sesebelisoa ka bowena. - Kenya BDF ea tšebetso ea 'mele eo mesebetsi ea sebele e abetsoeng eona.
- Kenya BAR "0" ho tsoela pele ho menu ea teko.
- Kenya khetho ea 7 ho thusa SR-IOV bakeng sa sesebelisoa sa hajoale.
- Kenya palo ea lits'ebetso tse tla bulela sesebelisoa sa hajoale.
- Kenya khetho ea 8 ho etsa tlhahlobo ea lihokelo bakeng sa ts'ebetso e 'ngoe le e 'ngoe e lumelletsoeng e abetsoeng tšebetso ea 'mele. Sesebelisoa sa tlhahlobo ea sehokelo se tla etsa hore memori e 100 e ngole ka dword e le 'ngoe ea data ebe e bala data hape bakeng sa ho e hlahloba. Sesebelisoa se tla hatisa palo ea lits'ebetso tse hlōlehileng tekong ea lihokelo qetellong ea tlhahlobo.
7. Ka terminal e ncha, tsamaisa lspci -d 1172: | grep -c "Altera" taelo ea ho netefatsa palo ea li-PF le VFs. Sephetho se lebelletsoeng ke kakaretso ea palo ea mesebetsi ea 'mele le palo ea mesebetsi ea sebele.
IP-tile Avalon Streaming IP bakeng sa PCI Express Design
Example User Guide Archives
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
ISO
9001:2015
Ngodisitsoe
Nalane ea Tokomane ea Tokomane ea Intel P-Tile Avalon
Phallela ka thata IP bakeng sa PCIe Design Example Bukana ea Mosebelisi
| Tokomane Version | Intel Quartus Prime Version | IP Version | Liphetoho |
| 2021.10.04 | 21.3 | 6.0.0 | Fetola litlhophiso tse tšehetsoeng bakeng sa moralo oa SR-IOV example ho tloha ho Gen3 x16 EP le Gen4 x16 EP ho ea ho Gen3 x8 EP le Gen4 x8 EP ho Tlhaloso ea Mosebetsi bakeng sa Single Root I/O Virtualization (SR-IOV) Design Example karolo. E kentse tšehetso bakeng sa Intel Stratix 10 DX P-tile Production FPGA Development Kit ho Hlahisa Design Ex.ample karolo. |
| 2021.07.01 | 21.2 | 5.0.0 | E tlositse li-waveform tsa ketsiso bakeng sa moralo oa PIO le SR-IOV examptse tsoang karolong ea Ho etsisa Moqapi Example. E ntlafalitse taelo ea ho hlahisa BDF karolong Ho tsamaisa PIO Design Example. |
| 2020.10.05 | 20.3 | 3.1.0 | E tlositse karolo ea Registers ho tloha ho moralo oa Avalon Streaming examples ha ba na rejisetara ea taolo. |
| 2020.07.10 | 20.2 | 3.0.0 | E kenyellelitsoe li-waveforms tsa ketsiso, litlhaloso tsa linyeoe tsa liteko le litlhaloso tsa sephetho sa tlhahlobo bakeng sa mohlala oa moraloamples. Litaelo tse ekelitsoeng tsa papiso bakeng sa simulator ea ModelSim ho Simulating ea Design Example karolo. |
| 2020.05.07 | 20.1 | 2.0.0 | E ntlafalitse sehlooho sa tokomane ho Intel FPGA P-Tile Avalon e phallela IP bakeng sa PCI Express Design Example Bukana ea Mosebelisi ho kopana le litataiso tse ncha tsa ho reha mabitso. E ntlafalitse taelo ea ho etsisa mokhoa oa VCS. |
| 2019.12.16 | 19.4 | 1.1.0 | E ekelitsoeng SR-IOV moralo example tlhaloso. |
| 2019.11.13 | 19.3 | 1.0.0 | E kentse Gen4 x8 Endpoint le Gen3 x8 Endpoint lethathamong la litlhophiso tse tšehetsoeng. |
| 2019.05.03 | 19.1.1 | 1.0.0 | Tokollo ea pele. |
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
ISO
9001:2015
Ngodisitsoe
Online Version
Romella Maikutlo
ID: 683038
UG-20234
Phetolelo: 2021.10.04
Litokomane / Lisebelisoa
 |
intel FPGA P-Tile Avalon Streaming IP bakeng sa PCI Express Design Example [pdf] Bukana ea Mosebelisi FPGA P-Tile, IP ea Phallo ea Avalon bakeng sa PCI Express Design Example, FPGA P-Tile Avalon Streaming IP bakeng sa PCI Express Design Example, FPGA P-Tile Avalon Streaming IP |
