Intel Interlaken 2nd Gen FPGA IP Release Notes
Interlaken (2nd Generation) Intel® FPGA IP Release Notes
Haeba molaetsa oa tokollo o sa fumanehe bakeng sa mofuta o itseng oa IP core, IP core ha e na liphetoho ho mofuta oo. Bakeng sa tlhaiso-leseling ka lintlafatso tsa IP ho fihla ho v18.1, sheba Lintlha tsa Phatlalatso tsa Intel Quartus Prime Design Suite. Liphetolelo tsa Intel® FPGA IP li tsamaisana le mefuta ea software ea Intel Quartus® Prime Design Suite ho fihlela v19.1. Ho qala ka Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP e na le leano le lecha la phetolelo. Nomoro ea Intel FPGA IP (XYZ) e ka fetoha ka mofuta o mong le o mong oa software ea Intel Quartus Prime. Phetoho ho:
- X e bontša phetoho e kholo ea IP. Haeba u nchafatsa software ea Intel Quartus Prime, u tlameha ho nchafatsa IP.
- Y e bonts'a IP e kenyelletsa likarolo tse ncha. Nchafatsa IP ea hau ho kenyelletsa likarolo tsena tse ncha.
- Z e bonts'a IP e kenyelletsa liphetoho tse nyane. Hlahisa IP ea hau bocha ho kenyelletsa liphetoho tsena.
- Lintlha tsa Phatlalatso ea Phatlalatso ea Intel Quartus Prime Design Suite
- Interlaken (2nd Generation) Intel FPGA IP User Guide
- Errata bakeng sa Interlaken (Moloko oa Bobeli) Intel FPGA IP Setsing sa Tsebo
- Interlaken (Moloko oa Bobeli) Intel Stratix 2 FPGA IP Design Example Bukana ea Mosebelisi
- Interlaken (Moloko oa Bobeli) Intel Agilex FPGA IP Design Example Bukana ea Mosebelisi
- Kenyelletso ea Intel FPGA IP Cores
Interlaken (Moloko oa 2) Intel FPGA IP v20.0.0
Lethathamo la 1. v20.0.0 2020.10.05
| Intel Quartus Prime Version | Tlhaloso | Tšusumetso |
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20.3 |
Ts'ehetso e ekelitsoeng bakeng sa sekhahla sa data sa 25.78125 Gbps. | - |
| Ts'ehetso ea litefiso tsa data e fetotsoe ho tloha ho 25.3 Gbps ho ea ho 25.28 Gbps le 25.8 Gbps ho ea ho 25.78125 Gbps. |
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Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.
Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
Interlaken (Moloko oa 2) Intel FPGA IP v19.3.0
Lethathamo la 2. v19.3.0 2020.06.22
| Intel Quartus Prime Version | Tlhaloso | Tšusumetso |
|
19.3.0 |
IP hona joale e tšehetsa karolo ea Interlaken Look-aside. | - |
| E kentsoe e ncha Numella mokhoa oa Interlaken Look-aside paramethara ho mohlophisi oa paramente ea IP. | O ka lokisa IP ka mokhoa oa Interlaken Look-aside. | |
| Khetho ea mokhoa oa ho fetisa parameter e tlositsoe ho mofuta oa hajoale oa software ea Intel Quartus Prime. |
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| E kenyellelitse 12.5 Gbps sekgahla sa data bakeng sa palo ea litselana 10 ho H- tile le E-tile (NRZ mode) IP core variations. |
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| E tlositse matšoao a latelang ho IP:
• rx_pma_data • tx_pma_data • e lapile • e lapile |
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| E kentse matšoao a macha a latelang:
• sop_cntr_inc1 • eop_cntr_inc1 • rx_xcoder_uncor_feccw • itx_ch0_xon • irx_ch0_xon • itx_ch1_xon • irx_ch1_xon • itx_valid • irx_valid • itx_idle • irx_idle • itx_ctrl • itx_credit • irx_credit |
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| E tlositsoe ho tse peli tse latelang 'mapeng oa ngoliso:
• 16'h40- TX_READY_XCVR • 16'h41- RX_READY_XCVR |
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| Tlhahlobo ea Hardware ea sebopeho sa example e se e fumaneha bakeng sa lisebelisoa tsa Intel Agilex™. | O ka leka sebopeho sa example ho Intel Agilex F- letoto la Transceiver-SoC Development Kit. | |
| U ka fetola sekhahla sa data le maqhubu a oache ea litšupiso tsa transceiver hore e be boleng bo fapaneng hanyane bakeng sa mohlala oa IP oa Interlaken (2nd Generation) o lebisitseng sesebelisoa sa Intel Stratix® 10 H-tile kapa E-tile. Sheba KDB ena ho fumana leseli la ho fetola sekhahla sa data. |
U ka khona ho etsa litefiso tsa data ho latela lithaele. |
Interlaken (Moloko oa 2) Intel FPGA IP v19.2.1
Lethathamo la 3. v19.2.1 2019.09.27
| Intel Quartus Prime Version | Tlhaloso | Tšusumetso |
|
19.3 |
Phatlalatso ea sechaba bakeng sa lisebelisoa tsa Intel Agilex tse nang le li-transceivers tsa E-tile. | - |
| E reha Interlaken (Moloko oa Bobeli) Intel Stratix 2 FPGA IP ho Interlaken (Moloko oa Bobeli) Intel FPGA IP |
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Interlaken (2nd Generation) Intel Stratix 10 FPGA IP v18.1 Update 1
Lethathamo la 4. Version 18.1 Update 1 2019.03.15
| Tlhaloso | Tšusumetso |
| Ts'ehetso ea mekhoa e mengata ea likarolo tse ngata. | - |
| E kentsoe Palo ea Likarolo paramethara. | - |
| • Ts'ehetso e ekelitsoeng bakeng sa metsoako ea sekhahla sa lane le data ka tsela e latelang:
- Bakeng sa lisebelisoa tsa Intel Stratix 10 L-tile: • Litsela tse 4 tse nang le litefiso tsa 12.5/25.3/25.8 Gbps • Litsela tsa 8 tse nang le litekanyetso tsa litsela tsa 12.5 Gbps - Bakeng sa lisebelisoa tsa Intel Stratix 10 H-tile: • Litsela tse 4 tse nang le litefiso tsa 12.5/25.3/25.8 Gbps • Litsela tse 8 tse nang le litefiso tsa 12.5/25.3/25.8 Gbps • Litsela tsa 10 tse nang le litekanyetso tsa 25.3 / 25.8 Gbps tsa litsela - Bakeng sa lisebelisoa tsa Intel Stratix 10 E-tile (NRZ): • Litsela tse 4 tse nang le litefiso tsa 6.25/12.5/25.3/25.8 Gbps • Litsela tse 8 tse nang le litefiso tsa 12.5/25.3/25.8 Gbps • Litsela tsa 10 tse nang le litekanyetso tsa 25.3 / 25.8 Gbps tsa litsela • Litsela tsa 12 tse nang le lebelo la 10.3125 Gbps |
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| • E kentse matshwao a latelang a matjha a ho fetisa mosebedisi:
— itx_eob1 — itx_eopbits1 — itx_chan1 |
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| • E kentse matshwao a latelang a seamohedi sa mosebedisi:
— irx_eob1 — irx_eopbits1 — irx_chan1 — irx_err1 — irx_err |
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Interlaken (2nd Generation) Intel Stratix 10 FPGA IP v18.1
Lethathamo la 5. Version 18.1 2018.09.10
| Tlhaloso | Tšusumetso | Lintlha |
| E reha tokomane thaele e le Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide |
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| E kenyellelitse mofuta oa papiso ea VHDL le tšehetso ea testbench bakeng sa mantlha ea IP ea Interlaken (2nd Generation). |
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| E kenyellelitse lirekoto tse ncha tse latelang ho mantlha ea IP: | ||
| • TX_READY_XCVR | ||
| • RX_READY_XCVR
• ILKN_FEC_XCODER_TX_ILLEGAL_ STATE |
- | Lirekoto tsena li fumaneha feela ka mefuta ea lisebelisoa tsa Intel Stratix 10 E-Tile. |
| • ILKN_FEC_XCODER_RX_ILLEGAL_ STATE |
Interlaken (Moloko oa 2) Intel FPGA IP v18.0.1
Lethathamo la 6. Version 18.0.1 July 2018
| Tlhaloso | Tšusumetso | Lintlha |
| Tšehetso e ekelitsoeng bakeng sa lisebelisoa tsa Intel Stratix 10 tse nang le li-transceivers tsa E-Tile. |
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| E kenyellelitse 53.125 Gbps sekgahla sa data bakeng sa lisebelisoa tsa Intel Stratix 10 E-Tile ka mokhoa oa PAM4. |
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| E kentse letšoao la oache mac_clkin bakeng sa lisebelisoa tsa Intel Stratix 10 E-Tile ka mokhoa oa PAM4 |
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Interlaken (Moloko oa 2) Intel FPGA IP v18.0
Lethathamo la 7. Version 18.0 May 2018
| Tlhaloso | Tšusumetso | Lintlha |
| E rehiloe lebitso la Interlaken IP core (Moloko oa 2) ho Interlaken (Moloko oa Bobeli) Intel FPGA IP ho latela Intel FPGA IP. |
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| E kenyellelitse 25.8 Gbps sekgahla sa data bakeng sa palo ea litselana 6 le 12. |
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| Tšehetso e ekelitsoeng bakeng sa Cadence Xcelium* Parallel simulator. |
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Interlaken IP Core (Moloko oa 2) v17.1
Lethathamo la 8. Version 17.1 November 2017
| Tlhaloso | Tšusumetso | Lintlha |
| Tokollo ea pele ho Intel FPGA IP Library. | - | - |
Lintlha Tse Amanang
Interlaken IP Core (Moloko oa Bobeli) Tataiso ea Mosebelisi
Interlaken (2nd Generation) Intel FPGA IP User Guide Archives
| Phetolelo ea Quartus | IP Core Version | Bukana ea Mosebelisi |
| 20.2 | 19.3.0 | Interlaken (Moloko oa Bobeli) FPGA IP User Guide |
| 19.3 | 19.2.1 | Interlaken (Moloko oa Bobeli) FPGA IP User Guide |
| 19.2 | 19.2 | Interlaken (Moloko oa Bobeli) FPGA IP User Guide |
| 18.1.1 | 18.1.1 | Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide |
| 18.1 | 18.1 | Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide |
| 18.0.1 | 18.0.1 | Interlaken (Moloko oa Bobeli) FPGA IP User Guide |
| 18.0 | 18.0 | Interlaken (2nd Generation) Intel FPGA IP User Guide |
| 17.1 | 17.1 | Interlaken IP Core (Moloko oa Bobeli) Tataiso ea Mosebelisi |
Liphetolelo tsa IP li tšoana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihla ho v19.1. Ho tsoa ho Intel Quartus Prime Design Suite software version 19.2 kapa hamorao, li-cores tsa IP li na le morero o mocha oa phetolelo ea IP. Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.
Litokomane / Lisebelisoa
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Intel Interlaken 2nd Gen FPGA IP Release Notes [pdf] Litaelo Lintlha tsa Phatlalatso tsa Interlaken 2nd Gen FPGA IP, Interlaken 2nd Gen, FPGA IP Release Notes |
