Intel F-Tile Interlaken FPGA IPDesign Example Bukana ea Mosebelisi

 

E ntlafalitsoe bakeng sa Intel® Quartus® Prime Design Suite: 21.4
Phetolelo ea IP: 3.1.0

1. Tataiso ea ho Qala ka Potlako

F-Tile Interlaken Intel® FPGA IP ea mantlha e fana ka benche ea teko ea ketsiso le moralo oa lisebelisoa tsa khale.ample e tšehetsang ho bokella le ho hlahloba hardware. Ha o hlahisa moqapi example, mohlophisi oa parameter o iketsetsa faele ea files bohlokoa ho etsisa, ho bokella, le ho leka moralo.

The testbench le moralo example e ts'ehetsa mokhoa oa NRZ le PAM4 bakeng sa lisebelisoa tsa F-tile.
F-Tile Interlaken Intel FPGA IP ea mantlha e hlahisa moralo oa examples bakeng sa metsoako e latelang e tšehetsoeng ea palo ea litselana le litefiso tsa data.

Letlapa la 1. IP e Tšehetsoeng Likopano tsa Palo ea Litsela le Litefiso tsa Data
Likopano tse latelang li tšehetsoa ho Intel Quartus® Prime Pro Edition software version 21.4. Tsohle
Metsoako e meng e tla tšehetsoa mofuteng o tlang oa Intel Quartus Prime Pro Edition.

 

Setšoantšo sa 1. Mehato ea Ntlafatso ea Moqapi Example

(1) Phapang ena e tšehetsa Mokhoa oa ho Sheba ka thoko oa Interlaken.
(2) Bakeng sa moralo oa tlhophiso ea litselana tse 10, F-tile e hloka litselana tse 12 tsa TX PMA ho etsa hore ho be le clocking transceiver clocking bakeng sa ho fokotsa skew ea kanale.

*Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

F-Tile Interlaken Intel FPGA IP core design example e tšehetsa likarolo tse latelang:

• Ka hare TX ho RX serial loopback mode
• E iketsetsa lipakete tsa boholo bo tsitsitseng
• Bokhoni ba ho hlahloba pakete ea mantlha
• Bokhoni ba ho sebelisa System Console ho hlophisa moralo bocha molemong oa ho etsa liteko hape

Setšoantšo sa 2. Setšoantšo sa Block Block se phahameng

Lintlha Tse Amanang

• F-Tile Interlaken Intel FPGA IP User Guide
• Lintlha tsa Phallo ea F-Tile Interlaken Intel FPGA IP

1.1. Litlhoko tsa Hardware le Software
Ho leka example design, sebelisa hardware le software tse latelang:

• Intel Quartus Prime Pro Edition software version 21.4
• System console e fumaneha ka software ea Intel Quartus Prime Pro Edition
• Simulator e tšehelitsoeng:
  - Synopsy* VCS*
  - Litlhaloso tsa VCS MX
  — Siemens* EDA ModelSim* SE kapa Questa*
  - Cadence * Xcelium *
• Intel Agilex™ I-Series Transceiver-SoC Development Kit

1.2. Ho Hlahisa Moralo
Setšoantšo sa 3. Mokhoa

Latela mehato ena ho hlahisa ex designample le testbench:

1. Ho software ea Intel Quartus Prime Pro Edition, tobetsa File ➤ Project Wizard e Ncha ho theha projeke e ncha ea Intel Quartus Prime, kapa tobetsa File ➤ Open Project ho bula morero o teng oa Intel Quartus Prime. Wizate e o kopa hore o hlalose sesebediswa.
2. Hlalosa lelapa la sesebelisoa sa Agilex ebe u khetha sesebelisoa se nang le F-Tile bakeng sa moralo oa hau.
3. Ho IP Catalog, fumana le ho penya habeli F-Tile Interlaken Intel FPGA IP. Ho hlaha fensetere e ncha ea IP Variant.
4. Hlalosa lebitso la boemo bo holimo bakeng sa phapang ea hau ea IP e tloaelehileng. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file bitsetsoe .ip.
5. Tobetsa OK. Mohlophisi oa parameter oa hlaha.

Setšoantšo sa 4. Example Design Tab

6. Ho tab ya IP, hlakisa maemo bakeng sa phapano ya mantlha ya IP ya hao.
7. Ho Example Design tab, khetha khetho ea Simulation ho hlahisa testbench. Khetha khetho ea Synthesis ho hlahisa moralo oa hardware example. U tlameha ho khetha bonyane khetho e le 'ngoe ea Simulation le Synthesis ho hlahisa moralo oa example.
8. Bakeng sa Hlahisa HDL Format, ka bobeli Verilog le VHDL kgetho e teng.
9. Bakeng sa Target Development Kit, khetha Agilex I-Series Transceiver-SOC Development Kit.

Tlhokomeliso: Ha u khetha khetho ea Development Kit, likabelo tsa phini li behoa ho latela nomoro ea karolo ea sesebelisoa sa Intel Agilex I-Series Transceiver-SoC Development Kit (AGIB027R31B1E2VR0) 'me e ka fapana le sesebelisoa seo u se khethileng. Haeba u batla ho lekola moralo ho hardware ho PCB e fapaneng, khetha khetho ea No development kit 'me u etse likabelo tse nepahetseng ho .qsf. file
10. Tobetsa Hlahisa Example Design. The Khetha Exampho hlaha fensetere ea Design Directory.
11. Haeba u batla ho fetola moralo examptsela ea directory kapa lebitso ho tsoa ho li-defaults tse bontšitsoeng (ilk_f_0_example_design), sheba tsela e ncha ebe u thaepa sebopeho se secha sa example lebitso la directory.
12. Tlanya OK.

Tlhokomeliso: Moetsong oa F-Tile Interlaken Intel FPGA IP example, SystemPLL e kenngoa ka bo eona, 'me e hokahane le F-Tile Interlaken Intel FPGA IP core. The SystemPLL hierarchy path in the design example ke:

example_design.test_env_inst.test_dut.dut.pll

The SystemPLL ka moralo example e arolelana oache e tšoanang ea 156.26 MHz joalo ka Transceiver.

1.3. Sebopeho sa Directory
F-Tile Interlaken Intel FPGA IP ea mantlha e hlahisa tse latelang files bakeng sa moralo
exampLe:
Setšoantšo sa 5. Sebopeho sa Directory

Lethathamo la 2. Moqapi oa lisebelisoa tsa thepa Example File Litlhaloso
Tsena files li hoample_installation_dir>/ilk_f_0_example_design directory.

Letlapa la 3. Testbench File Tlhaloso
Sena file e ka har'aample_installation_dir>/ilk_f_0_example_design/example_design/rtl directory.

Letlapa la 4. Litemana tsa Testbench
Tsena files li hoample_installation_dir>/ilk_f_0_example_design/example_design/testbench directory.

1.4. Ho etsisa Moqapi Example Testbench
Setšoantšo sa 6. Mokhoa

Latela mehato ena ho etsisa testbench:

1. Ka potlako ea taelo, fetola ho directory ea simulation ea testbench. Tsela ea directory keample_installation_dir>/example_design/testbench.
2. Matha sengoloa sa ketsiso bakeng sa simulator e tšehelitsoeng eo u e khethileng. Script e bokella le ho tsamaisa testbench ho simulator. Sengoliloeng sa hau se lokela ho lekola hore SOP le EOP li bapana ka mor'a hore papiso e felile.

Lethathamo la 5. Mehato ea ho Matha Ketsiso

3. Sekaseka liphello. Ketsiso e atlehileng e romella le ho amohela lipakete, 'me e bonts'a "Test PASSED".
The testbench bakeng sa moralo example phetha mesebetsi e latelang:

• E tiisa motheo oa F-Tile Interlaken Intel FPGA IP.
• E hatisa boemo ba PHY.
• E hlahloba khokahano ea metaframe (SYNC_LOCK) le meeli ea lentsoe (thibela).
  (LENTSO_LOTLA).
• E emetse hore litselana ka bomong li notleloe le ho lokisoa.
• E qala ho tsamaisa lipakete.
• E hlahloba lipalo-palo tsa liphutheloana:
  - Liphoso tsa CRC24
  - SOPs
  - EOPs

Tse latelang sample output e bonts'a ts'ebetso e atlehileng ea teko ea ketsiso:

Tlhokomeliso: Moqapi oa Interlaken example simulation testbench e romella lipakete tse 100 mme e amohela lipakete tse 100.

Tse latelang sample sephetho se bonts'a tlhahlobo e atlehileng ea ketsiso bakeng sa mokhoa oa Interlaken Look-aside:

1.5. Ho Kopanya le ho Hlophisa Moetso oa Hardware Example

1. Netefatsa hore example tlhahiso ea moralo e felile.
2. Ho software ea Intel Quartus Prime Pro Edition, bula morero oa Intel Quartus Primeample_installation_dir>/example_design.qpf>.
3. Holima Ho sebetsa menu, tobetsa Qala ho Kopanya.
4. Ka mor'a ho bokella ka katleho, a .sof file e fumaneha bukeng ea hau e boletsoeng.
   Latela mehato ena ho etsa lenaneo la hardware example moralo ho sesebelisoa sa Intel Agilex se nang le F-tile:
   a. Hokela Development Kit ho komporo ea moamoheli.
   b. Qala ts'ebeliso ea Clock Control, e leng karolo ea lisebelisoa tsa nts'etsopele. Beha maqhubu a macha bakeng sa moetso oa exampka tsela e latelang:
   • Bakeng sa mokhoa oa NRZ:
   - Si5391 (U18), OUT0: Beha boleng ba pll_ref_clk(3) ho latela tlhoko ea hau ea moralo.
   • Bakeng sa PAM mode:
   - Si5391 (U45), OUT1: Beha boleng ba pll_ref_clk(3) ho latela tlhoko ea hau ea moralo.
   - Si5391 (U19), OUT1: Beha boleng ba mac_pll_ref_clk(3) ho latela tlhoko ea hau ea moralo. c. Tobetsa Lisebelisoa ➤ Moetsi oa Lenaneo ➤ Ho Hlophisa Hardware.
   d. Khetha sesebelisoa sa ho etsa mananeo. Kenya Intel Agilex I-Series Transceiver-SoC Development Kit.
   e. Netefatsa seo Mokhoa e behiloe ho JTAG.
   f. Khetha sesebelisoa sa Intel Agilex I-Series ebe o tobetsa Kenya Sesebelisoa. Lenaneo le bonts'a setšoantšo sa likhokahano lipakeng tsa lisebelisoa tse botong ea hau.
   g. Sheba lebokose bakeng sa .sof.
   h. Sheba lebokose le ka har'a Lenaneo/Lokisa kholomo.
   ke. Tobetsa Qala.

1.6. Ho Lekola Moetso oa Hardware Example
Kamora ho bokella moralo oa F-tile Interlaken Intel FPGA IP example ho lokisa sesebelisoa sa hau, o ka sebelisa System Console ho hlophisa mantlha a IP le lirekoto tsa eona.

Latela mehato ena ho hlahisa Console ea Sisteme le ho leka moralo oa lisebelisoa tsa khaleampLe:

• Ha ho liphoso tsa CRC32, CRC24, le checker.
• Li-SOP tse fetisoang le li-EOP li lokela ho lumellana le li-SOP tse amoheloang le li-EOP.

Tse latelang sample sephetho se bonts'a tlhahlobo e atlehileng e etsoang ka mokhoa oa Interlaken:

Tse latelang sample sephetho se bonts'a tlhahlobo e atlehileng e etsoang ka mokhoa oa Interlaken Lookaside:

 

2. Moralo Example Tlhaloso

Moqapi example e bonts'a ts'ebetso ea mantlha ea IP ea Interlaken.

2.1. Moralo Example Likarolo
Example design e hokahanya lioache tsa litšupiso tsa sistimi le PLL le likarolo tse hlokahalang tsa moralo. Example design e hlophisa mantlha ea IP ka har'a mokhoa oa ka hare oa loopback mme e hlahisa lipakete ho sebopeho sa phetiso ea data ea mosebelisi ea IP core TX. IP core e romela lipakete tsena tseleng e ka hare ea loopback ka transceiver.

Kamora hore moamoheli oa mantlha oa IP a fumane lipakete tseleng ea loopback, e sebetsana le lipakete tsa Interlaken ebe e li fetisetsa ho sebopeho sa phetisetso ea data ea RX. Example design e lekola hore na lipakete li amohetse le ho fetisoa li ts'oana.

Moetso oa F-Tile Interlaken Intel FPGA IP example kenyeletsa likarolo tse latelang:

1. F-Tile Interlaken Intel FPGA IP ea mantlha
2. Pakete jenereithara le Pakete Checker
3. Reference F-Tile le System PLL Clocks Intel FPGA IP core

2.2. Moralo Example Phallo
F-Tile Interlaken Intel FPGA IP hardware moralo example phetha mehato e latelang:

1. Seta bocha F-tile Interlaken Intel FPGA IP le F-Tile.
2. Lokolla reset ho Interlaken IP (system reset) le F-tile TX (tile_tx_rst_n).
3. E lokisa F-tile Interlaken Intel FPGA IP ka mokhoa oa ka hare oa loopback.
4. Lokolla ho seta bocha ha F-tile RX (tile_rx_rst_n).
5. E romella liphutheloana tse ngata tsa Interlaken tse nang le data e boletsoeng esale pele e lefelloang ho sebopeho sa phetisetso ea data ea mosebelisi ea TX ea mantlha ea IP.
6. E hlahloba lipakete tse amohetsoeng ebe e tlaleha boemo. Sehlahlobi sa pakete se kenyellelitsoeng ho sebopeho sa hardware exampLe e fana ka lintlha tse latelang tsa ho hlahloba liphutheloana:
   • Lekola hore tatellano ea pakete e fetisoang e nepahetse.
   • Lekola hore na data e amohetsweng e tsamaellana le boleng bo lebeletsweng ka ho etsa bonnete ba hore palo ya ho qala pakete (SOP) le pheletso ya pakete (EOP) e tsamaellana ha data e ntse e fetiswa le ho amoheloa.

*Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

2.3. Lipontšo tsa Interface
Lethathamo la 6. Moqapi Example Lipontšo tsa Interface

2.4. Ngolisa 'mapa

Hlokomela:

• Moqapi ExampAterese ea register e qala ka 0x20** ha aterese ea mantlha ea IP ea Interlaken e qala ka 0x10**.
• Aterese ea ngoliso ea F-tile PHY e qala ka 0x30** ha aterese ea F-tile FEC e qala ka 0x40**. Ngoliso ea FEC e fumaneha feela ka mokhoa oa PAM4.
• Khouto ea ho kena: RO—Bala Feela, le RW—Bala/Ngola.
• System console e bala sebopeho sa exampe ngolisa le ho tlaleha boemo ba teko skrineng.

Lethathamo la 7. Moqapi Example Register Map

Lethathamo la 8. Moqapi Example Ngolisa 'mapa oa Interlaken Sheba-kathoko Design Example
Sebelisa 'mapa ona oa rejisetara ha u etsa moralo oa example ka Enable Interlaken Look-aside Mode parameter e butswe.

2.5. Hlahisa bocha
Ho F-Tile Interlaken Intel FPGA IP mantlha, o qala ho reset (reset_n=0) ebe o ts'oara ho fihlela IP core e khutlisa tumello ea ho seta bocha (reset_ack_n=0). Ka mor'a hore reset e tlosoe (reset_n=1), tumello ea ho tsosolosa e khutlela boemong ba eona ba pele (reset_ack_n=1). Ka moralo exampLeha ho le joalo, rst_ack_sticky registeri e boloka polelo ea tumello ea ho seta hape ebe e etsa hore ho tlosoe reset (reset_n=1). U ka sebelisa mekhoa e meng e lumellanang le litlhoko tsa hau tsa moralo.

Bohlokoa: Boemong bofe kapa bofe moo serial loopback e hlokahalang, o tlameha ho lokolla TX le RX tsa F-tile ka thoko ka tatellano e itseng. Sheba sengoloa sa console sa sistimi bakeng sa tlhaiso-leseling e batsi.

Setšoantšo sa 7. Khutlisa Tatelano ho Mokhoa oa NRZ

Setšoantšo sa 8. Seta hape Tatelano ho PAM4 Mode

 

3. F-Tile Interlaken Intel FPGA IP Design Example User Guide Archives

Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.

 

4. Nalane ea Phetoho ea Litokomane bakeng sa F-Tile Interlaken Intel FPGA IP Design Example Bukana ea Mosebelisi

 

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho fihlela joale
litlhaloso ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le litšebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.

 

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Intel F-Tile Interlaken FPGA IPDesign Example [pdf] Bukana ea Mosebelisi F-Tile Interlaken FPGA IPDesign Example

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