Intel Triple-Speed ​​Ethernet Agilex FPGA IP Design Example

Tataiso ea ho Qala ka Potlako

Triple-Speed ​​​​Ethernet Intel® FPGA IP bakeng sa Intel Agilex ™ e fana ka bokhoni ba ho hlahisa moralo oa khale.amples bakeng sa litlhophiso tse khethiloeng, tse u lumellang ho:

• Kopanya moralo ho fumana khakanyo ea tšebeliso ea sebaka sa IP le nako.
• Etsisa moralo ho netefatsa ts'ebetso ea IP ka papiso.
• Lekola moralo oa lisebelisoa tse sebelisang Intel Agilex I-Series Transceiver-SoC Development Kit.
• Ha o hlahisa ex designample, mohlophisi oa parameter o iketsetsa faele ea files bohlokoa ho etsisa, ho bokella, le ho leka moralo ho hardware.

Hlokomela: Tšehetso ea lisebelisoa ha e fumanehe hona joale ho Intel Quartus® Prime Pro Edition Software version 22.3.

Ntlafatso ea Stages bakeng sa Moqapi Example

Hlokomela: Ho Intel Quartus Prime Pro Edition Software version 22.3, patch e ea hlokahala ho qoba ho hloleha ho etsisa moetso oa khale.ample. Bakeng sa tlhaiso-leseling e batsi, sheba sehokelo sa KDB: Hobaneng ketsiso e hloleha bakeng sa Triple-Speed ​​Ethernet Intel FPGA IP Multiport Design Example?.

Lintlha Tse Amanang
Hobaneng ha ketsiso e hloleha bakeng sa Triple-Speed ​​Ethernet Intel® FPGA IP Multiport Design Example?.

Sebopeho sa Directory

Moralo oa Triple-Speed ​​Ethernet Intel FPGA IP example file li-directory li na le tse latelang tse hlahisitsoeng files bakeng sa 10/100/1000 Multiport Ethernet MAC Design Example e nang le 1000BASE-X/SGMII PCS le PMA e Kenyelitsoeng

• Sebopeho sa hardware le teko files (moralo oa hardware example) li fumaneha hoample_dir>/hardware_test_design.
• Ketsiso files (testbench bakeng sa ketsiso feela) li tengample_dir>/example_testbench.
• Moqapi oa ho bokella feela example e tengample_dir>/ compilation_test_design.
• Teko ea ho bokella le meralo ea liteko tsa Hardware e sebelisoa files hoample_dir>/ex_tse/common.

Sebopeho sa Directory bakeng sa Moralo Example

Letlapa la 1. Triple-Speed ​​Ethernet Intel FPGA IP Testbench File Tlhaloso

Directory/File	Tlhaloso
Testbench le Simulation Files
<design_example_dir>/example_testbench/ basic_avl_tb_top_mac_pcs.sv	Testbench ea boemo bo holimo file. Testbench e tiisa DUT mme e tsamaisa mesebetsi ea Verilog HDL ho hlahisa le ho amohela lipakete.
Litemana tsa Testbench
<design_example_dir>/example_testbench/ run_vsim_mac_pcs.sh	Sengoloa sa ModelSim ho tsamaisa testbench.
e tsoela pele…

Directory/File	Tlhaloso
<design_example_dir>/example_testbench/ run_vcs_mac_pcs.sh	Sengoliloeng sa Synopsy* VCS ho tsamaisa benche ea liteko.
<design_example_dir>/example_testbench/ run_vcsmx_mac_pcs.sh	Sengoloa sa Synopsys VCS MX (se kopantsoeng le Verilog HDL le System Verilog le VHDL) ho tsamaisa benche ea liteko.
<design_example_dir>/example_testbench/ run_xcelium_mac_pcs.sh	Sengoloa sa Xcelium* ho tsamaisa testbench.

Letlapa la 2. Triple-Speed ​​Ethernet Intel FPGA IP Hardware Design Example File Tlhaloso

Directory/File	Tlhaloso
<design_example_dir>/hardware_test_design/ altera_eth_tse_hw.qpf	Morero oa mantlha oa Intel Quartus file.
<design_example_dir>/hardware_test_design/ altera_eth_tse_hw.qsf	Litlhophiso tsa projeke ea Intel Quartus Prime file.
<design_example_dir>/hardware_test_design/ altera_eth_tse_hw.sdc	Litšitiso tsa Moqapi oa Synopsys files. U ka li kopitsa le ho li fetola files bakeng sa moralo oa hau oa Intel Stratix® 10.
<design_example_dir>/hardware_test_design/ altera_eth_tse_hw.v	Moralo oa maemo a holimo oa Verilog HDL example file.
<design_example_dir>/hardware_test_design/ common/	Moetso oa li-hardware example tšehetso files.

Ho Hlahisa Moqapi Example

Mokhoa oa ho Hlahisa Moralo Example

Example Design Tab ho Triple-Speed ​​Ethernet Intel FPGA IP Parameter Editor

Latela mehato ena ho hlahisa sebopeho sa hardware example le testbench:

• Ho software ea Intel Quartus Prime Pro Edition, tobetsa File ➤ Project Wizard e Ncha ho theha projeke e ncha ea Quartus Prime, kapa File ➤ Open Project ho bula morero o teng oa Quartus Prime. Wizate e o kopa hore o hlalose sesebediswa.
• Khetha lelapa la sesebelisoa sa Intel Agilex ebe u khetha sesebelisoa se nang le LVDS.
• Tobetsa Qetella ho koala wizate.
• Ho IP Catalogue, fumana ebe u khetha Interface Protocol ➤ Ethernet ➤ 1G Multirate
• Ethernet ➤ Triple-Speed ​​Ethernet Intel FPGA IP. Ho hlaha fensetere e ncha ea IP Variation.
• Hlalosa lebitso la boemo bo holimo bakeng sa phapang ea hau ea IP e tloaelehileng. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file bitsetsoe .ip.
• Tobetsa OK. Bahlophisi ba li-parameter baa hlaha.
• Ho hlahisa sebopeho sa mohlalaample, khetha mohlala oa moraloample seta esale pele ho tsoa laebraring ea Presets ebe o tobetsa Etsa kopo. Ha u khetha moralo, sisteme e itlhahisa ka bo eona li-parameter tsa IP bakeng sa moralo. Mohlophisi oa paramethara o beha ka bohona liparamente tse hlokahalang ho hlahisa moralo oa example. Se ke oa fetola li-parameter tse seng li setiloe ho tab ea IP.
• Bakeng sa Example Design Files, khetha Simulation kgetho ho hlahisa testbench, kapa Synthesis kgetho ho hlahisa hardware moralo example.
• Tlhokomeliso: U tlameha ho khetha bonyane khetho e le 'ngoe ho hlahisa sebopeho sa example.
• Ho Example Design tab, tlas'a Format ea HDL e hlahisitsoeng, khetha Verilog HDL kapa VHDL.
• Tlas'a Target Development Kit, khetha Agilex I-Series Transceiver-SoC Development Kit (AGIB027R31B1E2VR0) kapa khetha None.
• Tobetsa Example Design: “mohlalaample_design" konopo. The Khetha Exampho hlaha fensetere ea Design Directory.
• Haeba u batla ho fetola moralo examptsela ea directory kapa lebitso ho tsoa ho li-defaults tse bontšitsoeng (eth_tse_0_example_design), sheba tsela e ncha ebe u thaepa sebopeho se secha sa examplebitso la directory (ample_dir>).
• Tobetsa OK.

Moqapi Example Li-Parameters

Mekhahlelo ho Example Design Tab

Paramethara	Tlhaloso
Kgetha Moralo	E fumaneha example meralo bakeng sa litlhophiso tsa paramethara ea IP.
Example Design Files	The files ho hlahisa bakeng sa mokhahlelo o fapaneng oa ntlafatso. • Ketsiso—e hlahisa se hlokahalang files bakeng sa ho etsisa exampmoralo. • Synthesis-e hlahisa motsoako files. Sebelisa tsena files ho bokella moralo ho software ea Intel Quartus Prime Pro Edition bakeng sa tlhahlobo ea lisebelisoa le ho etsa tlhahlobo ea nako e tsitsitseng.
Hlahisa File Sebopeho	Sebopeho sa RTL files bakeng sa papiso — Verilog kapa VHDL.
Khetha Boto	Hardware e tšehelitsoeng bakeng sa ts'ebetsong ea moralo. Ha u khetha boto ea nts'etsopele ea Intel FPGA, the Sesebediswa se reriloeng ke eona e ts'oanang le sesebelisoa se ho Development Kit. Haeba lethathamo lena le le sieo, ha ho na boto e tšehetsoeng bakeng sa likhetho tseo u li khethang. Agilex I-Series Transceiver-SoC Development Kit: Khetho ena e u lumella hore u leke moqapi oa khaleample ho lisebelisoa tse khethiloeng tsa Intel FPGA IP. Khetho ena e khetha ka bo eona Sesebediswa se reriloeng ho bapisa sesebelisoa ho Intel FPGA IP ntshetsopele kit. Haeba tlhahlobo ea boto ea hau e na le kereiti e fapaneng ea sesebelisoa, o ka fetola sesebelisoa se shebiloeng. Ha ho letho: Khetho ena ha e kenyelle likarolo tsa hardware bakeng sa ex designample.

Ho etsisa Triple-Speed ​​Ethernet Intel FPGA IP Design Example Testbench

Mokhoa oa ho Etsisa Example Testbench

Latela mehato ena ho etsisa testbench:

• Fetolela bukeng ea simulation ea testbenchample_dir>/ example_testbench.
• Matha sengoloa sa ketsiso bakeng sa simulator e tšehelitsoeng eo u e khethileng. Script e bokella le ho tsamaisa testbench ho simulator. Sheba tafole Mehato ea ho etsisa Testbench.

Mehato ea ho etsisa Testbench

Moetsisi	Litaelo
ModelSim*	Moleng oa taelo, thaepa vsim -do run_vsim_mac_pcs.do. Haeba u khetha ho etsisa ntle le ho hlahisa ModelSim GUI, thaepa vsim -c -do run_vsim_mac_pcs.do.
Synopsys VCS*/ VCS MX	Moleng oa taelo, thaepa sh run_vcs_mac_pcs.sh kapa sh run_vcsmx_mac_pcs.sh.
Xcelium	Moleng oa taelo, thaepa sh run_xcelium_mac_pcs.sh.

• Sekaseka liphello. Testbench e atlehileng e romela lipakete tse leshome, e amohela palo e lekanang ea lipakete, 'me e bontša molaetsa o latelang.

Ho Kopanya le ho Hlophisa Moralo Example ho Hardware

Ho bokella moralo oa hardware example 'me u e hlophise sesebelisoa sa hau sa Intel Agilex, latela mehato ena:

• Netefatsa moralo oa hardware example moloko o felile.
• Ho software ea Intel Quartus Prime Pro Edition, bula morero oa Intel Quartus Primeample_dir>/hardware_test_design/ altera_eth_tse_hw.qpf.
• Ho menu ea Processing, tobetsa Start Compilation.
• Ka mor'a ho bokella ka katleho, a.sof file e fumaneha kaample_dir>/hardwarde_test_design directory

10/100/1000 Multiport Ethernet MAC Design Example e nang le 1000BASE-X/SGMII PCS le PMA e Kenyelitsoeng

Moqapi ona example e bonts'a tharollo ea Ethernet bakeng sa lisebelisoa tsa Intel Agilex tse sebelisang Triple-Speed ​​Ethernet IP. O ka hlahisa moralo ho tsoa ho ExampLetlapa la Moralo la mohlophisi oa paramethara ea Triple-Speed ​​Ethernet IP. Ho hlahisa moralo exampLeha ho le joalo, u tlameha ho qala ka ho beha litekanyetso tsa paramethara bakeng sa phapano ea IP eo u ikemiselitseng ho e hlahisa sehlahisoa sa hau sa ho qetela. Ho hlahisa mohlala oa moraloample etsa kopi ea IP. The testbench le hardware design example sebelisa kopi ea IP e le sesebelisoa se tlas'a teko (DUT). Haeba o sa behe boleng ba paramethara bakeng sa DUT ho tsamaisana le boleng ba paramethara sehlahiswang sa hao sa ho qetela, moralo wa ex.ampseo u se hlahisang ha se sebelise phapang ea IP eo u e rerileng.

Likaroloana

• E hlahisa example bakeng sa Triple-Speed ​​Ethernet Multiport Ethernet MAC ntle le Internal FIFO le PCS e nang le LVDS I/O e sebelisang likanale tse ngata tse arolelanoang FIFO.
• E hlahisa sephethephethe tseleng ea phetisetso mme e netefatsa data e fumanoeng ka transceiver LVDS I / O loopback ea kantle.
• Tx le RX serial ea ka ntle ea loopback mode ka LVDS I/O.
• E ts'ehetsa feela loopback ea kantle.
• E ts'ehetsa likou tse 'ne feela.

Litlhoko tsa Hardware le Software

• Intel e sebelisa lisebelisoa tse latelang le software ho leka moralo oa exampka sistimi ea Linux:
• Software ea Intel Quartus Prime Pro Edition
• ModelSim, VCS, VCS MX, le Xcelium simulators

Tlhaloso ea Ts'ebetso

Likarolo tsa Moqapi

Karolo	Tlhaloso
Triple-Speed ​​Ethernet Intel FPGA IP	Triple-Speed ​​Ethernet Intel FPGA IP (altera_eth_tse) e thehiloe ka tlhophiso e latelang: • Litlhophiso tsa mantlha: —   Phapang ea Konokono: 10/100/1000Mb Ethernet MAC le 1000BASE-X/SGMII PCS —   Sebelisa FIFO ea ka hare: Ha ea khethoa —   Palo ea likou:4 —   Mofuta oa transceiverTlhaloso: LVDS I/O • Likhetho tsa MAC: —   Numella tšehetso ea MAC 10/100 halofo ea duplex: E khethiloe —   Lumella loopback ea lehae ho MII/GMII: E khethiloe —   Numella liaterese tsa tlatsetso tsa MAC tsa unicast: Ha ea khethoa —   Kenyelletsa lipalo tsa lipalo: E khethiloe —   Lumella lipalo-palo tsa li-byte tsa 64-bit: Ha ea khethoa —   Kenyelletsa li-hashtable tsa multicast: Ha ea khethoa —   Lokisetsa lihlooho tsa pakete ho moeli oa 32-bit: Ha ea khethoa —   Numella taolo ea phallo ea duplex e felletseng: E khethiloe —   Lumella ho lemoha ha VLAN: Ha ea khethoa —   Lumella ho lemoha pakete ea boselamose: E khethiloe —   Kenyelletsa mojule oa MDIO (MDC/MDIO): E khethiloe —   Sebaka sa ho arola oache:50 • Nakoamp Likhetho: —   Lumella linakoampng: Ha ea khethoa • Likhetho tsa PCS/Transceiver: —   Lumella borokho ba SGMII: E khethiloe
Moreki Logic	E hlahisa le ho beha leihlo lipakete tse rometsoeng kapa tse amoheloang ka IP.
Ethernet Traffic Controller	E laoloa ka Avalon® segokanyimmediamentsi sa sebolokigolo.
JTAG ho Avalon-mapped interface Address Decoder	Fetolela JTAG Lipontšo tsa Avalon memory-mapped interface.

Oache le Seta Botjha Lipontšo

Letshwao	Tataiso	Bophara	Tlhaloso
ref_clk	Kenyeletso	1	Oache ea litšupiso tsa ho fihlella li khanna le oache ea boemo ba boemo ba MAC FIFO. Beha oache ho 100 MHz.
iopll_refclk	Kenyeletso	1	Oache ea litšupiso ea 125 MHz bakeng sa 1.25 Gbps serial LVDS I/O interface.

Ketsiso

Sehlahisoa sa tlhahlobo ea mohlala se etsa mehato e latelang:

• E qala moralo oa example lebelo la ho sebetsa la 1G.
• E lokisa lirejistara tsa Triple-Speed ​​Ethernet MAC le PCS.
• E emetse ho fihlela polelo ea tekanyo e nepahetseng ea lets'oao.
• E romella lipakete tseo e seng tsa PTP ho port 0.
• MAC RX port 0 e romella lipakete tse amoheloang ho MAC TX port 1.

Testbench

Block Diagram ea Design Example Multiport 10/100/1000Mb Ethernet MAC e nang le 1000BASE-X/SGMII PCS e nang le LVDS I/O Simulation Testbench

Sephetho sa Teko ea Ketsiso ea VCS Simulator

Nalane ea Phetoho ea Tokomane bakeng sa Triple-Speed Ethernet Intel FPGA IP Intel Agilex Design Example Bukana ea Mosebelisi

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
2022.12.09	22.3	21.1.0	Tokollo ea pele.

Litokomane / Lisebelisoa

Intel Triple-Speed ​​Ethernet Agilex FPGA IP Design Example [pdf] Bukana ea Mosebelisi Triple-Speed ​​Ethernet Agilex FPGA IP Design Example, Triple-Speed, Ethernet Agilex FPGA IP Design Example, IP Design Example

Litšupiso

• Bukana ea Mosebelisi