Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example
Tataiso ea ho Qala ka Potlako
The Low Latency E-Tile 40G Ethernet Intel® FPGA IP core e fana ka teko ea ho etsisa le moqapi oa hardware ex.ample e tšehetsang ho bokella le ho hlahloba hardware. Ha o hlahisa moqapi example, Intel Quartus® Prime IP parameter editor e iketsetsa eona files bohlokoa ho etsisa, ho bokella, le ho leka moralo ho hardware. Ntle le moo, o ka khoasolla moralo o hlophisitsoeng oa lisebelisoa ho lisebelisoa tsa Intel tse ikhethileng bakeng sa tlhahlobo ea ts'ebetso. Intel FPGA IP e boetse e kenyelletsa ex compilation-feelaample projeke eo u ka e sebelisang ho hakanya kapele sebaka sa mantlha sa IP le nako. The Low Latency E-Tile 40G Ethernet Intel FPGA IP e tšehetsa moralo example moloko o nang le mefuta e mengata ea liparamente. Leha ho le joalo, moqapi exampLes ha e koahele likarolo tsohle tse ka khonehang tsa Low Latency E-Tile 40G Ethernet Intel FPGA IP Core.
Mehato ea Ntlafatso ea Moqapi Example
Lintlha Tse Amanang
- Low Latency E-Tile 40G Ethernet Intel FPGA IP User Guide
Bakeng sa lintlha tse qaqileng ka Low Latency E-Tile 40G Ethernet IP. - Low Latency E-Tile 40G Ethernet Intel FPGA IP Release Notes
Lintlha tsa IP Release Notes li thathamisa liphetoho tsa IP tokollong e itseng.
Ho Hlahisa Moqapi Example
Tsamaiso
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
Example Design Tab ho Low Latency E-Tile 40G Ethernet Parameter Editor
Khetha Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit ho hlahisa moralo oa khale.ample bakeng sa lisebelisoa tsa Intel Stratix® 10. Khetha Agilex F-Series Transceiver-SoC Development Kit ho hlahisa moralo oa mohlalaample bakeng sa lisebelisoa tsa Intel Agilex™.
Latela mehato ena ho hlahisa sebopeho sa hardware example le testbench:
- Ho software ea Intel Quartus Prime Pro Edition, tobetsa File ➤ Setsebi se Secha sa Morero
ho theha projeke e ncha ea Intel Quartus Prime, kapa File ➤ Open Project ho bula projeke e teng ea Intel Quartus Prime software. Wizate e o kopa ho hlakisa lelapa la sesebelisoa le sesebelisoa.
Hlokomela: Moqapi oa mohlalaample overwrites kgetho le sesebediswa ka shebiloeng boto. U hlakisa boto e shebiloeng ho tsoa ho menu ea moralo oa example dikgetho ho Example Design tab (Mohato oa 8). - Ho IP Catalog, fumana 'me u khethe Low Latency E-Tile 40G Ethernet Intel FPGA IP. Ho hlaha fensetere e ncha ea IP Variation.
- Hlalosa lebitso la boemo bo holimo bakeng sa IP ea hau ea tloaelo. Intel Quartus Prime IP parameter editor e boloka maemo a fapaneng a IP ho a file bitsetsoe .ip.
- Tobetsa OK. IP parameter editor ea hlaha.
- Ho tab ea IP, hlakisa li-parameter tsa IP ea hau ea mantlha.
Hlokomela: Moralo oa Low Latency E-Tile 40G Ethernet Intel FPGA IP example ha e etsise ka nepo mme ha e sebetse ka nepo haeba o hlakisa e 'ngoe ea liparamente tse latelang:- Bulela selelekela sa ho feta
- Nako e itokiselitseng e behiloe ho boleng ba 3
- Lumella ho kenya TX CRC ho tingoe
- Ho Example Design tab, tlas'a Example Design Files, nolofalletsa khetho ea Simulation ho hlahisa testbench, 'me u khethe khetho ea Synthesis ho hlahisa moqapi oa thepa feela le oa hardware ex.amples.
Hlokomela: Ho Example Design tab, tlas'a Generated HDL Format, ke Verilog HDL feela e fumanehang. Setsi sena sa IP ha se tšehetse VHDL. - Tlas'a Target Development Kit khetha Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit kapa Agilex F-series Transceiver-SoC Development Kit.
Hlokomela: Thepa ea nts'etsopele eo u e khethang e hlakola khetho ea sesebelisoa ho Mohato- Sesebelisoa sa sepheo sa Intel Stratix 10 E-tile ke 1SG280LU3F50E3VGS1.
- Sepheo sa sesebelisoa sa Intel Agilex E-tile ke AGFB014R24A2E2VR0.
- Tobetsa Hlahisa Example konopo ea Design. Khetha Exampho hlaha fensetere ea Design Directory.
- Haeba u batla ho fetola moralo examptsela ea directory kapa lebitso ho tsoa ho li-defaults tse bontšitsoeng (alt_e40c3_0_example_design), sheba tsela e ncha ebe u thaepa sebopeho se secha sa examplebitso la directory (ample_dir>).
- Tobetsa OK.
Lintlha Tse Amanang
- IP Core Parameters
E fana ka lintlha tse ling mabapi le ho etsa IP ea hau ea mantlha. - Intel Stratix 10 E-Tile TX Signal Integrity Development Kit
- Intel Agilex F-Series FPGA Development Kit
Moqapi Example Li-Parameters
Mekhahlelo ho Example Design Tab
| Paramethara | Tlhaloso |
| Kgetha Moralo | E fumaneha example meralo bakeng sa litlhophiso tsa paramethara ea IP. Ha u khetha moralo ho tsoa laebraring ea Preset, sebaka sena se bonts'a moralo o khethiloeng. |
| Example Design Files | The files ho hlahisa bakeng sa mokhahlelo o fapaneng oa ntlafatso.
• Ketsiso- e hlahisa tse hlokahalang files bakeng sa ho etsisa exampmoralo. • Synthesis-e hlahisa motsoako files. Sebelisa tsena files ho bokella moralo ho software ea Intel Quartus Prime Pro Edition bakeng sa tlhahlobo ea lisebelisoa le ho etsa tlhahlobo ea nako e tsitsitseng. |
| Hlahisa File Sebopeho | Sebopeho sa RTL files bakeng sa papiso — Verilog kapa VHDL. |
| Khetha Boto | Hardware e tšehelitsoeng bakeng sa ts'ebetsong ea moralo. Ha u khetha boto ea nts'etsopele ea Intel, the Sesebediswa se reriloeng ke eona e ts'oanang le sesebelisoa se ho Development Kit.
Haeba lethathamo lena le le sieo, ha ho na boto e tšehetsoeng bakeng sa likhetho tseo u li khethang. Agilex F-Series Transceiver-SoC Development Kit: Khetho ena e u lumella hore u leke moqapi oa khaleample ho lisebelisoa tse khethiloeng tsa Intel FPGA IP. Khetho ena e khetha ka bo eona Sesebediswa se reriloeng Setšoantšo sa AGFB014R24A2E2VR0. Haeba tlhahlobo ea boto ea hau e na le kereiti e fapaneng ea sesebelisoa, o ka fetola sesebelisoa se shebiloeng. |
| e tsoela pele… | |
| Paramethara | Tlhaloso |
| Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit: Khetho ena e u lumella hore u leke moqapi oa khaleample ho lisebelisoa tse khethiloeng tsa Intel FPGA IP. Khetho ena e khetha ka bo eona Sesebediswa se reriloeng Setšoantšo sa 1ST280EY2F55E2VG Haeba tlhahlobo ea boto ea hau e na le kereiti e fapaneng ea sesebelisoa, o ka fetola sesebelisoa se shebiloeng.
Ha ho letho: Khetho ena ha e kenyelle likarolo tsa hardware bakeng sa ex designample. |
Sebopeho sa Directory
The Low Latency E-Tile 40G Ethernet IP core design example file li-directory li na le tse latelang tse hlahisitsoeng files bakeng sa moralo example.
Sebopeho sa Directory bakeng sa Moetso o Hlatsoeng Example
- Ketsiso files (testbench bakeng sa ketsiso feela) li tengample_dir>/example_testbench.
- Mohlala oa ho kopanya feelaample design e tengample_dir>/ compilation_test_design.
- Sebopeho sa hardware le teko files (moralo oa hardware example) li fumaneha hoample_dir>/hardware_test_design
Directory le File Litlhaloso
| File Mabitso | Tlhaloso |
| eth_ex_40g.qpf | Morero oa mantlha oa Intel Quartus file. |
| eth_ex_40g.qsf | Litlhophiso tsa projeke ea Intel Quartus Prime file. |
| e tsoela pele… | |
| File Mabitso | Tlhaloso |
| eth_ex_40g.sdc | Synopsy* Litšitiso tsa Moqapi file. U ka kopitsa le ho fetola sena file bakeng sa moralo oa hau oa Low Latency E-Tile 40G Ethernet Intel FPGA IP. |
| eth_ex_40g.srf | Molao oa khatello ea molaetsa oa Intel Quartus Prime file. |
| eth_ex_40g.v | Moralo oa maemo a holimo oa Verilog HDL example file. |
| eth_ex_40g_clock.sdc | Litšitiso tsa Moqapi oa Synopsys file bakeng sa lioache. |
| tloaelehileng/ | Moetso oa li-hardware example tšehetso files. |
| hwtest/main.tcl | Ka sehloohong file bakeng sa ho fihlella System Console. |
Ho Etsisa Moralo Example Testbench
O ka bokella le ho etsisa moralo ka ho sebelisa mongolo oa ketsiso ho tsoa ho taelo ea taelo.
- Ka potlako ea taelo, fetola buka ea ho sebetsa hoample_dir>/example_testbench.
- Matha sengoloa sa ketsiso bakeng sa simulator e tšehelitsoeng eo u e khethileng. Script e bokella le ho tsamaisa testbench ho simulator
Litaelo tsa ho etsisa Testbench
| Moetsisi | Litaelo |
| ModelSim* | Moleng oa taelo, thaepa vsim -do run_vsim.do.
Haeba u khetha ho etsisa ntle le ho hlahisa ModelSim GUI, thaepa vsim -c -do run_vsim.do. Hlokomela: Li-simulator tsa ModelSim-AE le ModelSim-ASE ha li khone ho etsisa motheo ona oa IP. U tlameha ho sebelisa simulator e 'ngoe e tšehelitsoeng ea ModelSim joalo ka ModelSim SE. |
| VCS* | Moleng oa taelo, thaepa sh run_vcs.sh |
| Tlhaloso: VCS MX | Moleng oa taelo, thaepa sh run_vcsmx.sh.
Sebelisa mongolo ona ha moralo o na le Verilog HDL le System Verilog e nang le VHDL. |
| NCSim | Moleng oa taelo, thaepa sh run_ncsim.sh |
| Xcelium* | Moleng oa taelo, thaepa sh run_xcelium.sh |
Ketsiso e atlehileng e qetella ka molaetsa o latelang: Ketsiso e Fetiloe. kapa Testbench e phethiloe. Ka mor'a ho qeta ka katleho, u ka sekaseka liphetho.
Ho Kopanya le ho Hlophisa Moralo Example ho Hardware
Intel FPGA IP core parameter editor e u lumella ho bokella le ho lokisa moralo oa example ho khithi ea ntlafatso e reriloeng
Ho bokella le ho lokisa sebopeho sa exampka hardware, latela mehato ena:
- Qala software ea Intel Quartus Prime Pro Edition ebe u khetha Ho sebetsa ➤ Qala Kopano ho hlophisa moralo.
- Ka mor'a hore u hlahise ntho ea SRAM file .sof, latela mehato ena ho hlophisa moralo oa hardware example sesebelisoa sa Intel:
- Khetha Lisebelisoa ➤ Setsebi.
- Ho "Programmer", tobetsa "Hardware Setup".
- Khetha sesebelisoa sa ho etsa mananeo.
- Khetha 'me u kenye boto ea Intel TX sebokeng sa hau sa Intel Quartus Prime Pro Edition.
- Netefatsa hore Mode e setetsoe ho JTAG.
- Khetha sesebelisoa sa Intel ebe o tobetsa Add Device. Lenaneo le bonts'a setšoantšo sa li-block tsa likhokahano lipakeng tsa lisebelisoa tse botong ea hau.
- Moleng le .sof ea hau, hlahloba lebokose la .sof.
- Bulela Lenaneo/Configure kgetho bakeng sa .sof.
- Tobetsa Qala.
Lintlha Tse Amanang
- Kopano e Eketsehileng bakeng sa Moralo oa Hierarchical le oa Sehlopha
- Lisebelisoa tsa lisebelisoa tsa Intel FPGA
Ho Fetola Sesebediswa Se Sebeletsoeng ho Hardware Design Example
Haeba u khethile Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit e le sesebelisoa seo u se batlang, Low Latency E-Tile 40G Ethernet Intel FPGA IP core e hlahisa lisebelisoa tsa khale.ample moralo oa sesebelisoa sa sepheo sa 1ST280EY2F55E2VG. Haeba u khethile Agilex F-Series Transceiver-SoC Development Kit e le sesebelisoa seo u se batlang, Low Latency E-Tile 40G Ethernet Intel FPGA IP core e hlahisa lisebelisoa tsa khale.ample moralo oa sesebelisoa sa sepheo sa AGFB014R24A2E2VR0. Sesebediswa se hlahisitsweng se ka nna sa fapana ho se sebediswang se ho khiti ya hao ya ntshetsopele. Ho fetola sesebediswa shebiloeng ka hardware moralo hao example, latela mehato ena:
- Qala software ea Intel Quartus Prime Pro Edition 'me u bule projeke ea tlhahlobo ea hardware file /hardware_test_design/eth_ex_40g.qpf.
- Ho menu ea likabelo, tobetsa Sesebediswa. Lebokose la puisano la Sesebelisoa lea hlaha.
- Ka har'a lebokose la puisano la Sesebediswa, khetha tafole ea sesebelisoa e thehiloeng ho E-tile e ts'oanang le nomoro ea karolo ea sesebelisoa ho kit ea hau ea ntlafatso. Sheba sehokelo sa lisebelisoa tsa nts'etsopele ho Intel websaete bakeng sa tlhaiso-leseling e batsi.
- Ho hlaha molaetsa ha o khetha sesebelisoa, joalo ka ha ho bonts'itsoe setšoantšong se ka tlase. Khetha Che ho boloka likabelo tsa phini tse hlahisitsoeng le likabelo tsa I/O.
Intel Quartus Prime Prompt bakeng sa Khetho ea Sesebelisoa
- Etsa moralo o felletseng oa moralo oa hau.
Hona joale o ka leka moralo ho hardware ea hau.
Lintlha Tse Amanang
- Intel Stratix 10 E-Tile TX Signal Integrity Development Kit
- Intel Agilex F-Series FPGA Development Kit
Ho etsa liteko tsa Low Latency E-Tile 40G Ethernet Intel FPGA IP Design ho Hardware
Kamora hore o hlophise Low Latency E-Tile 40G Ethernet Intel FPGA IP core design ex.ampLe 'me u e hlophise sesebelisoa sa hau sa Intel, u ka sebelisa System Console ho hlophisa motheo oa IP le lirekoto tsa eona tsa mantlha tsa Native PHY IP. Ho bulela System Console le ho leka moralo oa hardware example, latela mehato ena:
- Ho software ea Intel Quartus Prime Pro Edition, khetha Lisebelisoa ➤ Lisebelisoa tsa Tsamaiso ea Ts'ebetso ➤ System Console ho qala komporo ea sistimi.
- Fensetereng ea Tcl Console, thaepa cd hwtest ho fetola directory ho /hardware_test_design/hwtest.
- Tlanya source main.tcl ho bula khokahanyo ho JTAG monghadi.
Moetso o eketsehileng mohlalaampLitaelo li teng ho hlophisa motheo oa IP:
- chkphy_boemo: E bonts'a maqhubu a oache le boemo ba senotlolo sa PHY.
- chkmac_stats: E bonts'a boleng ho li-counters tsa lipalo tsa MAC.
- clear_all_stats: E hlakola lisebelisoa tsa lipalo tsa IP tsa mantlha.
- start_pkt_gen: E qala jenereithara ea pakete.
- stop_pkt_gen: E emisa jenereithara ea pakete.
- sys_reset_digital_analog: Sesebelisoa sa reset.
- loop_on: E bulela serial loopback ea kahare
- loop_off: E tima "loopback" ea ka hare.
- reg_bala : E khutlisa boleng ba rejisete ea mantlha ea IP ho .
- reg_ngola : E ngola ho aterese ea mantlha ea IP atereseng .
Latela mokhoa oa teko karolong ea Hardware Testing ea ex designamp'me u shebe liphetho tsa liteko ho System Console.
Lintlha Tse Amanang
Ho sekaseka le ho lokisa meralo ka System Console
Moqapi Example Tlhaloso
Moqapi oa E-tile o thehiloeng ho 40G Ethernet example e bonts'a mesebetsi ea Low Latency E-Tile 40G Ethernet Intel FPGA IP core, e nang le E-tile based transceiver interface e lumellanang le IEEE 802.3ba e tloaelehileng ea CAUI-4. O ka hlahisa moralo ho tsoa ho Example Design tab ho Low Latency E-Tile 40G Ethernet Intel FPGA IP parameter editor.
Ho hlahisa moralo exampLeha ho le joalo, u tlameha ho qala ka ho beha litekanyetso tsa paramethara bakeng sa phapano ea mantlha ea IP eo u ikemiselitseng ho e hlahisa sehlahisoa sa hau sa ho qetela. Ho hlahisa mohlala oa moraloampe etsa kopi ea mantlha ea IP; testbench le hardware design exampke sebelisa phapano ena joalo ka DUT. Haeba o sa behe boleng ba paramethara bakeng sa DUT ho tsamaisana le boleng ba paramethara sehlahiswang sa hao sa ho qetela, moralo wa ex.ampSeo u se hlahisang ha se sebelise phapang ea mantlha ea IP eo u e rerileng.
Hlokomela:
Testbench e bonts'a teko ea motheo ea IP core. Ha e reretsoe ho nka sebaka sa tikoloho e felletseng ea netefatso. U tlameha ho etsa netefatso e batsi haholoanyane ea moralo oa hau oa Low Latency E-Tile 40G Ethernet Intel FPGA IP ka papiso le ka har'a lisebelisoa.
Likaroloana
- E ts'ehetsa 40G Ethernet MAC/PCS IP core bakeng sa transceiver ea E-tile e sebelisang Intel Stratix 10 kapa sesebelisoa sa Intel Agilex.
- E tšehetsa selelekela sa ho feta le koetliso ea likhokahanyo.
- E hlahisa example e nang le likarolo tsa lipalo tsa lipalo tsa MAC.
- E fana ka testbench le script ketsiso.
Litlhoko tsa Hardware le Software
Ho leka example design, sebelisa hardware le software tse latelang:
- Software ea Intel Quartus Prime Pro Edition
- Console ea tsamaiso
- ModelSim, VCS, VCS MX, NCSim, kapa Xcelium Simulator
- Intel Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit kapa Intel Agilex F-series Transceiver-SoC Development Kit
Tlhaloso ea Ts'ebetso
Karolo ena e hlalosa 40G Ethernet MAC/PCS IP core ho sebelisa sesebelisoa sa Intel ho transceiver e thehiloeng ho E-tile. Tabeng ea phetisetso, MAC e amohela liforeimi tsa bareki ebe e kenya inter-packet gap (IPG), selelekela, qalo ea foreime delimiter (SFD), padding, le CRC bits pele e li fetisetsa ho PHY. PHY e kenyelletsa foreimi ea MAC joalo ka ha ho hlokahala bakeng sa phetiso e tšepahalang ho media ho isa pheletsong e hole. Ka tataiso ea ho amohela, PHY e fetisetsa liforeimi ho MAC. MAC e amohela liforeimi ho tsoa ho PHY, e etsa licheke, e hlobola CRC, selelekela, le SFD, ebe e fetisetsa foreime e setseng ho moreki.
Ketsiso
Testbench e romela sephethephethe ka IP core, ho sebelisa lehlakore la phetisetso le ho amohela lehlakore la IP core.
Low Latency E-Tile 40G Ethernet Design Example Block Diagram
Moqapi oa ketsiso example teko ea boemo bo holimo file is basic_avl_tb_top.sv. Sena file e fana ka litšupiso tsa oache clk_ref ea 156.25 Mhz ho PHY. E kenyelletsa mosebetsi oa ho romella le ho amohela lipakete tse 10.
Low Latency E-Tile 40G Ethernet Core Testbench File Litlhaloso
| File Mabitso | Tlhaloso |
| Testbench le Simulation Files | |
| basic_avl_tb_top.sv | Testbench ea boemo bo holimo file. Testbench e tiisa DUT mme e tsamaisa mesebetsi ea Verilog HDL ho hlahisa le ho amohela lipakete. |
| basic_avl_tb_top_nc.sv | Testbench ea boemo bo holimo file e lumellana le simulator ea NCSim. |
| basic_avl_tb_top_msim.sv | Testbench ea boemo bo holimo file e lumellana le simulator ea ModelSim. |
| Litemana tsa Testbench | |
| run_vsim.do | Mongolo oa Mentor Graphics* ModelSim ho tsamaisa benche ea liteko. |
| run_vcs.sh | Mongolo oa Synopsys VCS ho tsamaisa testbench. |
| e tsoela pele… | |
| File Mabitso | Tlhaloso |
| run_vcsmx.sh | Mongolo oa Synopsys VCS MX (o kopantsoeng le Verilog HDL le System Verilog le VHDL) ho tsamaisa benche ea liteko. |
| run_ncsim.sh | Sengoloa sa Cadence NCSim ho tsamaisa testbench. |
| run_xcelium.sh | Sengoloa sa Cadence Xcelium ho tsamaisa testbench. |
Teko e atlehileng e bonts'a tlhahiso e netefatsang boitšoaro bo latelang:
- E emetse hore oache ea RX e lule
- Ho hatisa boemo ba PHY
- Ho romela lipakete tse 10
- Ho amohela lipakete tse 10
- E hlahisa "Testbench e felile."
Tse latelang sample output e bonts'a ts'ebetso e atlehileng ea teko ea ketsiso:
- #E emetse ho lokisoa ha RX
- #RX deskew e notletsoe
- #RX lane lane e notletsoe
- #TX e lumelletsoe
- #**Ho romella Pakete ea 1…
- #**Ho romella Pakete ea 2…
- #**Ho romella Pakete ea 3…
- #**Ho romella Pakete ea 4…
- #**Ho romella Pakete ea 5…
- #**Ho romella Pakete ea 6…
- #**Ho romella Pakete ea 7…
- #**E amohetse Pakete ea 1…
- #**Ho romella Pakete ea 8…
- #**E amohetse Pakete ea 2…
- #**Ho romella Pakete ea 9…
- #**E amohetse Pakete ea 3…
- #**Ho romella Pakete ea 10…
- #**E amohetse Pakete ea 4…
- #**E amohetse Pakete ea 5…
- #**E amohetse Pakete ea 6…
- #**E amohetse Pakete ea 7…
- #**E amohetse Pakete ea 8…
- #**E amohetse Pakete ea 9…
- #**E amohetse Pakete ea 10…
Lintlha Tse Amanang
Ho Etsisa Moralo Example Testbench leqepheng la 7
Hardware Testing
Moqapi oa lisebelisoa tsa thepa example, o ka hlophisa mantlha ea IP ka har'a mokhoa oa ka hare oa serial loopback mme o hlahise sephethephethe lehlakoreng la phetisetso le khutlelang ka lehlakoreng le amohelang.
Low Latency E-Tile 40G Ethernet IP Hardware Design Example High Level Block Diagram
Moralo oa Hardware oa Low Latency E-Tile 40G Ethernet example kenyeletsa likarolo tse latelang:
- Low Latency E-Tile 40G Ethernet Intel FPGA IP ea mantlha.
- Monahano oa bareki o hokahanyang mananeo a mantlha a IP, le tlhahiso ea lipakete le ho hlahloba.
- IOPLL ho hlahisa oache ea 100 MHz ho tloha ho 50 MHz ho ea ho sebopeho sa lisebelisoa tsa khale.ample.
- JTAG molaoli ea buisanang le Intel System Console. U buisana le logic ea bareki ka System Console.
Latela mokhoa o ho sehokelo sa tlhaiso-leseling se amanang ho leka sebopeho sa example ho hardware e khethiloeng.
Lintlha Tse Amanang
- Ho etsa liteko tsa Low Latency E-Tile 40G Ethernet Intel FPGA IP Design ho Hardware leqepheng la 9
- Ho sekaseka le ho lokisa meralo ka System Console
Teko ea ka hare ea Loopback
Etsa mehato ena ho etsa tlhahlobo ea ka hare ea loopback:
- Seta sistimi bocha.
sys_reset_digital_analog - Hlahisa maqhubu a oache le boemo ba PHY.
chkphy_boemo - Bulela teko ea ka hare ea loopback.
loop_on - Hlahisa maqhubu a oache le boemo ba PHY. The rx_clk e behiloe ho 312.5 MHz le
rx_pcs_ready e behiloe ho 1.
chkphy_boemo - Qala jenereithara ea pakete.
qala_pkt_gen - Emisa jenereithara ea pakete.
emisa_pkt_gen - Review palo ea lipakete tse fetisoang le tse amoheloang.
chkmac_stats - Koala teko ea ka hare ea loopback.
loop_off
Teko ea Kantle ea Loopback
Etsa mehato ena ho etsa tlhahlobo ea kantle ea loopback:
- Seta sistimi bocha.
sys_reset_digital_analog - Hlahisa maqhubu a oache le boemo ba PHY. The rx_clk e behiloe ho 312.5 MHz le
rx_pcs_ready e behiloe ho 1. chkphy_status - Qala jenereithara ea pakete.
qala_pkt_gen - Emisa jenereithara ea pakete.
emisa_pkt_gen - Review palo ea lipakete tse fetisoang le tse amoheloang.
chkmac_stats
Low Latency E-Tile 40G Ethernet Design Example Registers
Low Latency E-Tile 40G Ethernet Hardware Design Example Register Map
E thathamisa mekhahlelo ea rejisetara ea memori bakeng sa moralo oa hardware example. U fihlella lirekoto tsena ka mesebetsi ea reg_read le reg_write ho System Console.
| Lentsoe Offset | Mofuta oa Ngoliso |
| 0x300-0x3FF | PHY e ngolisa |
| 0x400-0x4FF | TX MAC e ngolisa |
| 0x500-0x5FF | RX MAC e ngolisa |
| 0x800-0x8FF | Lirekoto tsa Lipalo-palo - tataiso ea TX |
| 0x900-0x9FF | Lirekoto tsa Lipalo-palo - tataiso ea RX |
| 0x1000-1016 | Pakete ea Client e ngolisa |
Lingoliloeng tsa Bareki ba Pakete
U ka etsa moralo oa Hardware oa Low Latency E-Tile 40G Ethernet example ka ho etsa mananeo a ngoliso ea bareki.
| Addr | Lebitso | Bit | Tlhaloso | HW Reset Boleng | Phihlello |
| 0x1008 | Pakete ea Size Configure | [29:0] | Hlalosa boholo ba pakete ea phetisetso ka li-byte. Li-bits tsena li its'etleha ho ngoliso ea PKT_GEN_TX_CTRL.
• Bit [29:16]: Hlalosa moeli o ka holimo oa boholo ba pakete ka li-byte. Sena se sebetsa feela molemong oa ho eketsa. • Nyenyane [13:0]: - Bakeng sa mokhoa o tsitsitseng, likotoana tsena li totobatsa boholo ba pakete ea phetisetso ka li-byte. - Bakeng sa mokhoa oa ho eketsa, li-bits tsena li totobatsa li-byte tse ntseng li eketseha bakeng sa pakete. |
0x25800040 | RW |
| 0x1009 | Taolo ea Nomoro ea Pakete | [31:0] | Hlalosa palo ea lipakete tse lokelang ho fetisoa ho tsoa ho jenereithara ea pakete. | 0xA | RW |
| 0x1010 | PKT_GEN_TX_C TRL | [7:0] | • Bit [0]: E bolokiloe.
• Bit [1]: Pakete jenereithara tima bitana. Beha karolo ena ho boleng ba 1 ho tima jenereithara ea pakete, 'me u e khutlisetse ho boleng ba 0 ho bulela jenereithara ea pakete. • Bit [2]: E bolokiloe. • Bit [3]: E na le boleng ba 1 haeba IP core e le ka MAC loopback mode; e na le boleng ba 0 haeba moreki oa pakete a sebelisa jenereithara ea pakete. |
0x6 | RW |
| e tsoela pele… | |||||
| Addr | Lebitso | Bit | Tlhaloso | HW Reset Boleng | Phihlello |
| • Nyenyane [5:4]:
- 00: Mokhoa o sa reroang - 01: Mokhoa o tsitsitseng - 10: Mokhoa oa ho eketsa • Bit [6]: Beha sekhechana sena ho 1 ho sebelisa rejisetara ea 0x1009 ho tima jenereithara ea pakete ho latela palo e tsitsitseng ea lipakete tse lokelang ho fetisoa. Ho seng joalo, bit [1] ea PKT_GEN_TX_CTRL rejisetara e sebelisetsoa ho tima jenereithara ea pakete. • Nyenyane [7]: — 1: Bakeng sa phetiso ntle le lekhalo lipakeng tsa lipakete. — 0: Bakeng sa phetiso e nang le lekhalo le sa reroang lipakeng tsa lipakete. |
|||||
| 0x1011 | Aterese ea moo u eang e ka tlase ho li-bits tse 32 | [31:0] | Aterese ea moo e eang (ka tlase ho 32 bits) | 0x56780ADD | RW |
| 0x1012 | Aterese ea moo u eang ho li-bits tse 16 | [15:0] | Aterese ea moo e eang (kaholimo ho 16 bits) | 0x1234 | RW |
| 0x1013 | Aterese ea mohloli e ka tlase ho li-bits tse 32 | [31:0] | Aterese ea mohloli (ka tlase ho 32 bits) | 0x43210ADD | RW |
| 0x1014 | Aterese ea mohloli o kaholimo ho li-bits tse 16 | [15:0] | Aterese ea mohloli (li-bits tse ka holimo tse 16) | 0x8765 | RW |
| 0x1016 | PKT_CL_LOOPB ACK_RESET | [0] | MAC loopback reset. Beha boleng ba 1 ho seta botjha sebopeho sa example MAC loopback. | 1b0 | RW |
Lintlha Tse Amanang
Low Latency E-Tile 40G Ethernet Taolo le Litlhaloso tsa Ngoliso ea Boemo E hlalosa li-register tsa mantlha tsa IP tsa Latency E-Tile 40G Ethernet IP.
Moqapi Example Lipontšo tsa Interface
Low Latency E-Tile 40G Ethernet testbench e ikemetse 'me ha e hloke hore u khanne matšoao leha e le afe a ho kenya.
Low Latency E-Tile 40G Ethernet Hardware Design Example Lipontšo tsa Interface
| Letshwao | Tataiso | Maikutlo |
|
clk50 |
Kenyeletso |
Oache ena e tsamaisoa ke oscillator ea boto.
• Khanna ka 50 MHz ho Intel Stratix 10 board. • Khanna ka 100 MHz ho Intel Agilex board. Moetso oa hardware exampe tsamaisa oache ena ho kenya IOPLL sesebelisoa mme e hlophisa IOPLL ho khanna oache ea 100 MHz kahare. |
| clk_ref | Kenyeletso | Khanna ho 156.25 MHz. |
| e tsoela pele… | ||
| Letshwao | Tataiso | Maikutlo |
|
cpu_resetn |
Kenyeletso |
E tsosolosa motheo oa IP. E sebetsa tlase. E tsamaisa csr_reset_n ea lefats'e ka bophara ho ea ho IP core. |
| tx_serial[3:0] | Sephetho | Lintlha tsa seriale tsa Transceiver PHY. |
| rx_serial[3:0] | Kenyeletso | Transceiver PHY e kenya data ea seriale. |
|
mosebelisi [7:0] |
Sephetho |
Matšoao a boemo. Moetso oa hardware example e hokahanya likotoana tsena ho khanna li-LED holim'a boto e shebiloeng. Li-bits ka bomong li bonts'a boleng ba matšoao a latelang le boitšoaro ba oache:
• [0]: Letšoao la ho qala bocha ho IP core • [1]: Mofuta o arohaneng oa clk_ref • [2]: Mofuta o arohaneng oa clk50 • [3]: Mofuta o arohaneng oa 100 MHz boemo oache • [4]: tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready |
Lintlha Tse Amanang
Li-interfaces le Litlhaloso tsa Lipontšo E fana ka litlhaloso tse qaqileng tsa matšoao a mantlha a Low Latency E-Tile 40G Ethernet IP le li-interfaces tseo e leng tsa tsona.
Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.
| Intel Quartus Prime Version | IP Core Version | Bukana ea Mosebelisi |
| 20.1 | 19.1.0 | Low Latency E-Tile 40G Ethernet Design Example Bukana ea Mosebelisi |
Nalane ea Tokomane ea Tokomane bakeng sa Low Latency E-tile 40G Ethernet Design Example Bukana ea Mosebelisi
| Tokomane Version | Intel Quartus Prime Version | IP Version | Liphetoho |
| 2020.06.22 | 20.2 | 20.0.0 | Ts'ehetso ea lisebelisoa bakeng sa lisebelisoa tsa Intel Agilex. |
| 2020.04.13 | 20.1 | 19.1.0 | Phatlalatso ea Pele. |
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
Litokomane / Lisebelisoa
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intel Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example [pdf] Bukana ea Mosebelisi Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example, Low Latency, E-Tile 40G Ethernet Intel FPGA IP Design Example, Intel FPGA IP Design Example, IP Design Example |
