F-Tile DisplayPort FPGA IP Design Example
Bukana ea Mosebelisi
F-Tile DisplayPort FPGA IP Design Example
E ntlafalitsoe bakeng sa Intel® Quartus® Prime Design Suite: 22.2 IP Version: 21.0.1
DisplayPort Intel FPGA IP Design Example Quick Start Guide
Lisebelisoa tsa DisplayPort Intel® F-tile li na le benche e etsisang ea liteko le moralo oa Hardware o ts'ehetsang ho bokella le ho etsa liteko tsa hardware FPGA IP design ex.ampbakeng sa Intel Agilex™
DisplayPort Intel FPGA IP e fana ka moralo o latelang oa mohlalaamphanyane:
- DisplayPort SST parallel loopback ntle le mojule oa Pixel Clock Recovery (PCR).
- DisplayPort SST e tsamaisanang le loopback e nang le AXIS Video Interface
Ha o hlahisa ex designample, mohlophisi oa parameter o iketsetsa faele ea files bohlokoa ho etsisa, ho bokella, le ho leka moralo ho hardware.
Setšoantšo sa 1. Ntlafatso ea Stages
Lintlha Tse Amanang
- DisplayPort Intel FPGA IP User Guide
- Ho fallela ho Intel Quartus Prime Pro Edition
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.
*Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
ISO 9001:2015 E Ngolisitsoe
1.1. Sebopeho sa Directory
Setšoantšo sa 2. Sebopeho sa Directory
Lethathamo la 1. Moqapi Example Likarolo
| Liphutheli | Files |
| rtl/core | dp_core.ip |
| dp_rx. ip | |
| dp_tx. ip | |
| rtl/rx_phy | dp_gxb_rx/ ((Sebaka sa moaho sa DP PMA UX) |
| dp_rx_data_fifo . ip | |
| rx_top_phy . sv | |
| rtl/tx_phy | dp_gxb_rx/ ((Sebaka sa moaho sa DP PMA UX) |
| dp_tx_data_fifo.ip | |
| dp_tx_data_fifo.ip |
1.2. Litlhoko tsa Hardware le Software
Intel e sebelisa lisebelisoa tse latelang le software ho leka moralo oa exampLe:
Lisebelisoa
- Intel Agilex I-Series Development Kit
- DisplayPort Source GPU
- DisplayPort Sink (Monitor)
- Bitec DisplayPort FMC karete ea morali Revision 8C
- Lithapo tsa DisplayPort
Software
- Intel Quartus® Prime
- Synopsy* VCS Simulator
1.3. Ho Hlahisa Moralo
Sebelisa DisplayPort Intel FPGA IP parameter mohlophisi ho Intel Quartus Prime software ho hlahisa moralo oa example.
Setšoantšo sa 3. Ho Hlahisa Phallo ea Moqapi
- Khetha Tools ➤ IP Catalog, ebe u khetha Intel Agilex F-tile e le lelapa la sesebelisoa se shebiloeng.
Hlokomela: Moqapi example e tšehetsa feela lisebelisoa tsa Intel Agilex F-tile. - Ho IP Catalog, fumana le ho penya habeli DisplayPort Intel FPGA IP. Ho hlaha fensetere e ncha ea IP Variation.
- Hlalosa lebitso la boemo bo holimo bakeng sa IP ea hau ea tloaelo. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file bitsetsoe .ip.
- Khetha sesebelisoa sa Intel Agilex F-tile tšimong ea Sesebediswa, kapa boloka khetho ea kamehla ea Intel Quartus Prime software.
- Tobetsa OK. Mohlophisi oa parameter oa hlaha.
- Lokisa liparamente tse lakatsehang tsa TX le RX ka bobeli.
- Tlas'a Moralo Exampho tab, khetha DisplayPort SST Parallel Loopback Ntle le PCR.
- Khetha Simulation ho hlahisa testbench, 'me u khethe Synthesis ho hlahisa moralo oa hardware example. U tlameha ho khetha bonyane e 'ngoe ea likhetho tsena ho hlahisa sebopeho sa example files. Haeba u khetha ka bobeli, nako ea moloko e ba telele.
- Bakeng sa Target Development Kit, khetha Intel Agilex I-Series SOC Development Kit. Sena se etsa hore sesebelisoa sa shebiloeng se khethiloeng mohatong oa 4 se fetohe ho ts'oana le sesebelisoa ho kit ea nts'etsopele. Bakeng sa Intel Agilex I-Series SOC Development Kit, sesebelisoa sa kamehla ke AGIB027R31B1E2VR0.
- Tobetsa Hlahisa Example Design.
1.4. Ho Etsisa Moralo
Moetso oa DisplayPort Intel FPGA IP example testbench e etsisa moralo oa serial loopback ho tloha mohlala oa TX ho ea ho mohlala oa RX. Mojule oa jenereithara oa ka hare oa video o khanna mohlala oa DisplayPort TX mme tlhahiso ea video ea RX e hokahana le licheke tsa CRC ho testbench.
Setšoantšo sa 4. Phallo ea Ketsiso ea Moralo
- Eya ho foldara ea simulator ea Synopsy ebe u khetha VCS.
- Etsa mongolo oa ketsiso.
Mohloli vcs_sim.sh - Script e etsa Quartus TLG, e bokella le ho tsamaisa testbench ho simulator.
- Sekaseka sephetho.
Papiso e atlehileng e qetella ka papiso ea Mohloli le Sink SRC.
1.5. Ho Kopanya le ho Lekola Moralo
Setšoantšo sa 5. Ho bokella le ho etsisa Moralo
Ho bokella le ho etsa tlhahlobo ea pontšo ho hardware example design, latela mehato ena:
- Netefatsa hore hardware example tlhahiso ea moralo e felile.
- Qala software ea Intel Quartus Prime Pro Edition 'me u bule /quartus/agi_dp_demo.qpf.
- Tobetsa Ho sebetsa ➤ Qala ho Kopanya.
- Ka mor'a ho bokella ka katleho, software ea Intel Quartus Prime Pro Edition e hlahisa .sof file bukeng ea hau e boletsoeng.
- Hokela sehokelo sa DisplayPort RX kareteng ea morali ea Bitec mohloling oa kantle oa DisplayPort, joalo ka karete ea litšoantšo ho PC.
- Hokela sehokelo sa DisplayPort TX kareteng ea morali ea Bitec ho sesebelisoa sa sinki sa DisplayPort, joalo ka sehlahlobi sa video kapa sebali sa PC.
- Netefatsa hore li-switches tsohle tse botong ea ntlafatso li maemong a kamehla.
- Lokisa sesebelisoa sa Intel Agilex F-Tile se khethiloeng ka har'a boto ea nts'etsopele u sebelisa tlhahiso ea .sof file (Lisebelisoa ➤ Moqapi ).
- Sesebelisoa sa teba sa DisplayPort se bonts'a video e hlahisitsoeng mohloling oa video.
Lintlha Tse Amanang
Intel Agilex I-Series FPGA Development Kit Tataiso ea mosebelisi/
1.5.1. Ho nchafatsa ELF File
Ka tloaelo, ELF file e hlahisoa ha o hlahisa dynamic design example.
Leha ho le joalo, maemong a mang, o hloka ho nchafatsa ELF file haeba u fetola software file kapa tsosolosa dp_core.qsys file. E nchafatsa dp_core.qsys file e nchafatsa .sopcinfo file, e hlokang hore u tsosolose ELF file.
- Eya ho /software le ho hlophisa khoutu ha ho hlokahala.
- Eya ho /script 'me u phethe sengoloa se latelang: source build_sw.sh
• Ho Windows, batla 'me u bule Nios II Command Shell. Ho Nios II Command Shell, ea ho /script 'me u phethe mohloli build_sw.sh.
Hlokomela: Ho kenya tšebetsong script ho Windows 10, sistimi ea hau e hloka Windows Subsystems bakeng sa Linux (WSL). Bakeng sa tlhaiso-leseling e batsi mabapi le mehato ea ho kenya WSL, sheba ho Nios II Software Developer Handbook.
• Ho Linux, thakhola Moqapi oa Platform, 'me u bule Lisebelisoa ➤ Nios II Command Shell. Ho Nios II Command Shell, ea ho /script 'me u phethe mohloli build_sw.sh. - Etsa bonnete ba hore .elf file e hlahisoa ka /software/ dp_demo.
- Khoasolla tlhahiso ea .elf file ho kena ho FPGA ntle le ho khutlisa .sof file ka ho tsamaisa mongolo o latelang: nios2-download /software/dp_demo/*.elf
- Tobetsa konopo ea reset botong ea FPGA hore software e ncha e sebetse.
1.6. DisplayPort Intel FPGA IP Design Example Li-Parameters
Letlapa la 2. DisplayPort Intel FPGA IP Design Example tšitiso ea QSF bakeng sa Intel Agilex Ftile Device
| QSF Constrait |
Tlhaloso |
| set_global_assignment -lebitso VERILOG_MACRO “__DISPLAYPORT_support__=1” |
Ho tloha Quartus 22.2 ho ea pele, tšitiso ena ea QSF ea hlokahala ho nolofalletsa DisplayPort tloaelo ea SRC (Soft Reset Controller) ho phalla. |
Letlapa la 3. DisplayPort Intel FPGA IP Design Example Parameters bakeng sa Sesebelisoa sa Intel Agilex F-tile
| Paramethara | Boleng | Tlhaloso |
| Moqapi o Fumanehang Example | ||
| Kgetha Moralo | •Ha ho letho •DisplayPort SST Parallel Loopback ntle le PCR •DisplayPort SST Parallel Loopback e nang le AXIS Video Interface |
Khetha mohlala oa moraloample tla hlahisoa. •Ha ho letho: Ha ho na mohlala oa moraloample e fumaneha bakeng sa khetho ea hajoale ea parametha. •DisplayPort SST Parallel Loopback ntle le PCR: Moetso ona example e bonts'a loopback e ts'oanang ho tloha sinking ea DisplayPort ho ea mohloling oa DisplayPort ntle le mojule oa Pixel Clock Recovery (PCR) ha o bulela paramethara ea Numella Video Input Image Port. •DisplayPort SST Parallel Loopback with AXIS Video Interface: Moetso ona example e bonts'a loopback e ts'oanang ho tloha sinking ea DisplayPort ho ea mohloling oa DisplayPort ka sebopeho sa Video sa AXIS ha Enable Active Video Data Protocols e setetsoe ho AXIS-VVP Full. |
| Moqapi Example Files | ||
| Ketsiso | Bulehile, Tima | Bulela khetho ena ho etsa se hlokahalang files bakeng sa ketsiso testbench. |
| Synthesis | Bulehile, Tima | Bulela khetho ena ho etsa se hlokahalang files bakeng sa pokello ea Intel Quartus Prime le moralo oa lisebelisoa. |
| HDL Format e entsoeng | ||
| Hlahisa File Sebopeho | Verilog, VHDL | Khetha mofuta oo u o ratang oa HDL bakeng sa sebopeho se hlahisitsoeng sa example filebeha. Tlhokomeliso: Khetho ena e khetha feela sebopeho sa IP ea boemo bo holimo e hlahisitsoeng files. Tse ling kaofela files (mohlample testbenches le boemo bo holimo files bakeng sa pontšo ea hardware) li ka sebopeho sa Verilog HDL. |
| Setsi sa Nts'etsopele se reriloeng | ||
| Khetha Boto | •Ha ho Kit ea Ntlafatso •Intel Agilex I-Series Ntlafatso Kit |
Khetha boto bakeng sa moralo o lebisitsoeng oa mohlalaample. |
| Paramethara | Boleng | Tlhaloso |
| •No Development Kit: Khetho ena ha e kenyeletse likarolo tsohle tsa hardware bakeng sa ex designample. P core e beha likabelo tsohle tsa pini ho li-virtual pin. •Intel Agilex I-Series FPGA Development Kit: Khetho ena e ikhethela sesebelisoa se shebiloeng sa morero ho tsamaisana le sesebelisoa ho kit ena ea ntlafatso. U ka fetola sesebelisoa se shebiloeng u sebelisa parameter ea Change Target Device haeba boto ea hau e na le phapang e fapaneng ea lisebelisoa. IP core e beha likabelo tsohle tsa phini ho latela lisebelisoa tsa nts'etsopele. Tlhokomeliso: Moqapi oa Pele ExampLe ha e ea netefatsoa ka lisebelisoa tsa Hardware tokollong ena ea Quartus. •Custom Development Kit: Khetho ena e lumella moqapi exampe tla lekoa ho lisebelisoa tsa nts'etsopele ea motho oa boraro ka Intel FPGA. Ho ka 'na ha hlokahala hore u behe likabelo tsa phini u le mong. |
||
| Sesebediswa se reriloeng | ||
| Fetola Sesebediswa se Lebeletsweng | Bulehile, Tima | Bulela khetho ena 'me u khethe mofuta o ratoang oa sesebelisoa bakeng sa lisebelisoa tsa ntlafatso. |
Parallel Loopback Design Examples
Moetso oa DisplayPort Intel FPGA IP exampre bonts'a loopback e ts'oanang ho tloha mohlala oa DisplayPort RX ho ea ho DisplayPort TX ntle le mojule oa Pixel Clock Recovery (PCR).
Letlapa la 4. DisplayPort Intel FPGA IP Design Example bakeng sa Sesebelisoa sa Intel Agilex F-tile
| Moqapi Example | Khethollo | Sekhahla sa Lintlha | Mokhoa oa Channel | Mofuta oa Loopback |
| DisplayPort SST parallel loopback ntle le PCR | DisplayPort SST | RBR, HRB, HRB2, HBR3 | Simplex | E tšoana ntle le PCR |
| DisplayPort SST e tsamaisanang le loopback e nang le AXIS Video Interface | DisplayPort SST | RBR, HRB, HRB2, HBR3 | Simplex | E tsamaisana le AXIS Video Interface |
2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Likaroloana
Moetso oa SST o ts'oanang oa loopback exampre bonts'a phetiso ea video e le 'ngoe ho tloha siling ea DisplayPort ho ea mohloling oa DisplayPort.
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
ISO 9001:2015 E Ngolisitsoe
Setšoantšo sa 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback ntle le PCR
- Mofuteng ona, paramethara ea mohloli oa DisplayPort, TX_SUPPORT_IM_ENABLE, e buletsoe 'me ho sebelisoa sebopeho sa setšoantšo sa video.
- Sekoahelo sa DisplayPort se amohela video le kapa audio audio ho tsoa mohloling oa video o kantle joalo ka GPU ebe e e hlophisa hore e be sebopeho sa video se ts'oanang.
- Tlhahiso ea video e tebang ea DisplayPort e khanna ka kotloloho sebopeho sa video sa mohloli oa DisplayPort ebe e kenyelletsa sehokelo sa mantlha sa DisplayPort pele e fetisetsa ho sebali.
- IOPLL e khanna sinki ea DisplayPort le lioache tsa video tsa mohloli ka lebelo le tsitsitseng.
- Haeba sinki ea DisplayPort le mohloli oa MAX_LINK_RATE parameter e lokiselitsoe ho ba HBR3 'me PIXELS_PER_CLOCK e hlophisitsoe ho ba Quad, oache ea video e sebetsa ho 300 MHz ho tšehetsa 8Kp30 reiti (1188/4 = 297 MHz).
Setšoantšo sa 7. Intel Agilex F-tile DisplayPort SST Parallel Loopback le Video ea AXIS Sehokedi
- Phapang ena, mohloli oa DisplayPort le parameter ea sink, khetha AXIS-VVP FULL ho ENABLE ACTIVE VIDEO DATA PROTOCOLS ho nolofalletsa Axis Video Data Interface.
- Sekoahelo sa DisplayPort se amohela video le kapa audio audio ho tsoa mohloling oa video o kantle joalo ka GPU ebe e e hlophisa hore e be sebopeho sa video se ts'oanang.
- DisplayPort Sink e fetola phallo ea data ea video hore e be data ea video ea axis mme e tsamaisa sebopeho sa data sa video sa axis sa DisplayPort ka VVP Video Frame Buffer. DisplayPort Source e fetola data ea axis ea video hore e be sehokelo sa mantlha sa DisplayPort pele e fetisetsoa ho sebali.
- Phapang ena ea moralo, ho na le lioache tse tharo tsa mantlha tsa video, e leng rx/tx_axi4s_clk, rx_vid_clk, le tx_vid_clk. axi4s_clk e sebetsa ho 300 MHz bakeng sa li-module tsa AXIS ka Mohloli le Sink. rx_vid_clk e tsamaisa pipeline ea DP Sink Video ka 300 MHz (ho tšehetsa qeto efe kapa efe ho fihla ho 8Kp30 4PIPs), ha tx_vid_clk e tsamaisa DP Source Video pipeline ka lebelo la sebele la Pixel Clock (e arotsoeng ke PIPs).
- Mofuta ona oa boqapi o lokisa tx_vid_clk frequency ka I2C programming ho board ea SI5391B OSC ha moralo o bona phetoho ho qeto.
- Phapang ena ea moralo e bonts'a feela palo e tsitsitseng ea liqeto joalo ka ha e hlalositsoe ho software ea DisplayPort, e leng:
— 720p60, RGB
— 1080p60, RGB
— 4K30, RGB
— 4K60, RGB
2.2. Sekema sa ho Tlisa
Morero oa oache o bonts'a libaka tsa oache ho DisplayPort Intel FPGA IP moralo example.
Setšoantšo sa 8. Intel Agilex F-tile DisplayPort Transceiver clocking scheme
Letlapa la 5. Lipontšo tsa Scheme ea ho Tsupa
| Setšoantšo sa oache |
Tlhaloso |
| Setšoantšo sa SysPLL | F-tile System PLL e ka ba maqhubu leha e le afe a oache a aroloang ke System PLL bakeng sa maqhubu ao a tsoang. Moqaping ona example, system_pll_clk_link le rx/tx refclk_link li arolelana refclk e tšoanang ea 150 MHz SysPLL. |
| Setšoantšo sa oache | Tlhaloso |
| E tlameha ho ba oache ea mahala e hokahantsoeng ho tloha pineng ea oache ea transceiver e inehetseng ho koung ea oache ea Reference le System PLL Clocks IP, pele e hokahanya boema-kepe bo lumellanang le DisplayPort Phy Top. Tlhokomeliso: Bakeng sa mohlala ona oa moraloample, lokisa Clock Controller GUI Si5391A OUT6 ho 150 MHz. |
|
| system pll clk link | Nako e fokolang ea tlhahiso ea System PLL ho tšehetsa sekhahla sa DisplayPort ke 320 MHz. Moqapi ona example sebelisa 900 MHz (e phahameng ka ho fetisisa) maqhubu a tlhahiso e le hore SysPLL refclk e ka arolelanoa le rx/tx refclk_link e leng 150 MHz. |
| rx_cdr_refclk_link / tx_pll_refclk_link | Rx CDR le Tx PLL Link refclk e tsitsitseng ho 150 MHz ho ts'ehetsa sekhahla sa data sa DisplayPort. |
| rx_ls_clkout / tx_ls_clkout | DisplayPort Link Speed Clock ho tšupa konokono ea DisplayPort IP. Maqhubu a lekanang le Sekhahla sa Lintlha arola ka bophara ba data bo bapileng. ExampLe: Hangata = sekhahla sa data / bophara ba data = 8.1G (HBR3) / 40 bits = 202.5 MHz |
2.3. Ketsiso Testbench
Testbench ea simulation e etsisa DisplayPort TX serial loopback ho RX.
Setšoantšo sa 9. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram
Letlapa la 6. Likarolo tsa Testbench
| Karolo | Tlhaloso |
| Jenereithara ea Paterone ea Video | Jenereithara ena e hlahisa lipaterone tsa mebala eo u ka e hlophisang. U ka etsa parameterize ea nako ea sebopeho sa video. |
| Taolo ea Testbench | Sebaka sena se laola tatellano ea tlhahlobo ea papiso mme e hlahisa matšoao a hlokahalang a ts'usumetso ho mantlha ea TX. Setsi sa taolo ea testbench se boetse se bala boleng ba CRC ho tloha mohloling le ho teba ho etsa lipapiso. |
| RX Link Speed Clock Frequency Checker | Sehlahlobi sena se netefatsa hore na transceiver ea RX e fumaneng nako ea oache e lumellana le sekhahla sa data se lakatsehang. |
| TX Link Speed Clock Frequency Checker | Sehlahlobi sena se netefatsa hore na transceiver ea TX e fumaneng nako ea oache e lumellana le sekhahla sa data se lakatsehang. |
The simulation testbench e etsa linetefatso tse latelang:
Lethathamo la 7. Litefiso tsa Testbench
| Litekanyetso tsa Teko |
Netefatso |
| • Khokahano ea Koetliso ho Sekhahla sa Lintlha HBR3 • Bala direjista tsa DPCD ho bona hore na DP Status e beha le ho lekanya bobedi maqhubu a TX le RX Link Speed. |
E kopanya Frequency Checker ho lekanya lebelo la sehokelo tlhahiso ea maqhubu a oache ho tsoa ho transceiver ea TX le RX. |
| • Matha paterone ea video ho tloha TX ho ea ho RX. • Netefatsa CRC bakeng sa mohloli le sink ho hlahloba hore na lia lumellana |
• E hokahanya jenereithara ea mohlala oa video ho Mohloli oa DisplayPort ho hlahisa paterone ea video. • Taolo ea Testbench e latelang e bala ka bobeli Source le Sink CRC ho tsoa ho DPTX le DPRX rejisetara mme e bapisa ho netefatsa hore boleng ba CRC ka bobeli boa tšoana. Tlhokomeliso: Ho etsa bonnete ba hore CRC e baloa, o tlameha ho nolofalletsa paramethara ea tlhahlobo ea tšehetso ea CTS. |
Nalane ea Phetoho ea Litokomane bakeng sa F-Tile DisplayPort Intel FPGA IP Design Example Bukana ea Mosebelisi
| Tokomane Version | Intel Quartus Prime Version | IP Version | Liphetoho |
| 2022.09.02 | 22. | 20.0.1 | •E fetotsoe sehlooho sa tokomane ho tsoa ho DisplayPort Intel Agilex F-Tile FPGA IP Design Example Tataiso ea mosebelisi ho F-Tile DisplayPort Intel FPGA IP Design Example Bukana ea Mosebelisi. •Moqapi oa Video oa AXIS o nolofalitsoeng Example variant. •E tlositse moralo oa Static Rate le ho e nkela sebaka ka Multi Rate Design Example. •E tlositse molaetsa ho DisplayPort Intel FPGA IP Design Example Tataiso ea ho Qala ka Potlako e reng mofuta oa software oa Intel Quartus Prime 21.4 o tšehetsa feela Preliminary Design Examples. •Ho bea palo e nepahetseng sebakeng sa Sebopeho sa Directory. •E kentse karolo Ho hlahisa ELF bocha File tlas'a Ho Kopanya le ho Lekola Moralo. •E ntlafalitse karolo ea Hardware le Software Requirements hore e kenyelle lisebelisoa tse ling ditlhoko. |
| 2021.12.13 | 21. | 20.0.0 | Tokollo ea pele. |
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.
*Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
ISO 9001:2015 E Ngolisitsoe
Online Version
Romella Maikutlo
UG-20347
ID: 709308
Phetolelo: 2022.09.02
Litokomane / Lisebelisoa
 |
Intel F-Tile DisplayPort FPGA IP Design Example [pdf] Bukana ea Mosebelisi F-Tile DisplayPort FPGA IP Design Example, F-Tile DisplayPort, DisplayPort, FPGA IP Design Example, IP Design Example, UG-20347, 709308 |
