Intel UG-01155 IOPLL FPGA IP Core

E ntlafalitsoe bakeng sa Intel® Quartus® Prime Design Suite: 18.1

IOPLL Intel® FPGA IP Core User Guide

IOPLL Intel® FPGA IP ea mantlha e u lumella ho hlophisa litlhophiso tsa Intel Arria® 10 le Intel Cyclone® 10 GX I/O PLL.

IOPLL IP core e tšehetsa likarolo tse latelang:

• E ts'ehetsa mekhoa e tšeletseng e fapaneng ea ho fana ka maikutlo a oache: maikutlo a tobileng, a kantle, a tloaelehileng, mohloli oa synchronous, zero delay buffer, le mokhoa oa LVDS.
• E hlahisa mats'oao a ho fihla ho lioache tse robong bakeng sa lisebelisoa tsa Intel Arria 10 le Intel CycloneM 10 GX.
• Fetoha lipakeng tsa lioache tse peli tsa litšupiso.
• E ts'ehetsa kenyeletso e haufi ea PLL (adjpllin) ho hokela le PLL e nyolohang ka mokhoa oa PLL cascading.
• E hlahisa ho Qala Memori File (.mif) mme e lumella PLL dynamicVreconfiguration.
• E ts'ehetsa phetoho ea karolo e matla ea PLL.

Lintlha Tse Amanang

• Kenyelletso ea Intel FPGA IP Cores
  E fana ka lintlha tse ling mabapi le Intel FPGA IP cores le parameter editor.
• Mekhoa ea ts'ebetso leqepheng la 9
• Lioache tse hlahisoang leqepheng la 10
• Reference Clock Switchover leqepheng la 10
• PLL-to-PLL Cascading leqepheng la 11
• IOPLL Intel FPGA IP Core User Guide Archives leqepheng la 12

E fana ka lethathamo la litataiso tsa basebelisi bakeng sa mefuta e fetileng ea IOPLL Intel FPGA IP core.

Sesebelisoa sa Tšehetso ea Lelapa

IOPLL IP ea mantlha e tšehetsa feela malapa a lisebelisoa tsa Intel Arria 10 le Intel Cyclone 10 GX.

IOPLL IP Core Parameters

The IOPLL IP core parameter editor e hlaha sehlopheng sa PLL sa IP Catalog.

Paramethara	Boleng ba Molao	Tlhaloso
Lelapa la Sesebelisoa	Intel Arria 10, Intel Leholiotsoana la 10 GX	E totobatsa lelapa la sesebelisoa.
Karolo	—	E totobatsa sesebelisoa se lebisitsoeng.
Lebelo la Potlako	—	E totobatsa lebelo la sesebelisoa se lebisitsoeng.
Mokhoa oa PLL	Palo-N PLL	E hlalosa mokhoa o sebelisoang bakeng sa mantlha oa IPLL IP. Khetho ea molao feela ke palo e feletseng-N PLL. Haeba o hloka PLL e fokolang, o tlameha ho sebelisa fPLL Intel Arria 10/Cyclone 10 FPGA IP core.
Reference Clock Frequency	—	E totobatsa khafetsa ea ho kenya oache ea ho kenya, refclk, ho MHz. Boleng ba kamehla ke 100.0 MHz. Bonyane le boholo ba boleng bo itšetlehile ka sesebelisoa se khethiloeng.
Numella Boema-kepe ba Lintho Tse Koetsoeng	Bulela kapa Tima	Bulela ho bulela sebaka se notletsoeng.
Numella liparamente tsa oache ea tlhahiso ea 'mele	Bulela kapa Tima	Bulela ho kenya li-parameter tsa PLL tsa 'mele ho e-na le ho bolela hore na ke nako efe eo u e batlang.
Mokhoa oa ts'ebetso	tsepameng, maikutlo a kantle, tloaelehileng, mohlodi synchronous, buffer ea ho lieha ho feta, kapa lvds	E hlalosa ts'ebetso ea PLL. Opereishene ea kamehla ke tsepameng mokgoa. • Haeba o kgetha faele ya tsepameng mokhoa, PLL e fokotsa bolelele ba tsela ea maikutlo ho hlahisa jitter e nyenyane ka ho fetisisa e ka khonehang tlhahisong ea PLL. Liphello tsa nako e ka hare-hare le tsa ka ntle tsa PLL li fetoloa ka mohato mabapi le ho kenya letsoho ho PLL. Ka mokhoa ona, PLL ha e lefelle marang-rang leha e le afe a oache. • Haeba o kgetha faele ya tloaelehileng mode, PLL e lefella tieho ea marang-rang a oache ea ka hare e sebelisoang ke tlhahiso ea oache. Haeba PLL e boetse e sebelisetsoa ho khanna pinana ea ho hlahisa oache e ka ntle, phetoho ea karolo e tsamaellanang ea lets'oao ho pin ea tlhahiso e etsahala. • Haeba o kgetha faele ya mohlodi synchronous mokhoa, tieho ea oache ho tloha ho phini ho ea ho rejisetara ea ho kenya ea I/O e tsamaisana le tieho ea data ho tloha ho phini ho ea ho rejisetara ea ho kenya ea I/O. • Haeba o kgetha faele ya maikutlo a kantle mode, o tlameha ho hokela kou ea fbclk ho phini ea ho kenya. Khokahano ea boemo ba boto e tlameha ho hokela phini ea ho kenya le boema-kepe ba oache ea kantle, fboutclk. Boema-kepe ba fbclk bo tsamaisana le oache ea ho kenya. • Haeba o kgetha faele ya buffer ea ho lieha ho feta mokhoa, PLL e tlameha ho fepa phini ea tlhahiso ea oache e kantle le ho lefella tieho e hlahisitsoeng ke phini eo. Letšoao le bonoang pineng le hokahanngoa le oache e kenang. Phallo ea oache ea PLL e hokahana le boema-kepe ba altbidir mme e khanna zdbfbclk joalo ka boema-kepe ba tlhahiso. Haeba PLL e boetse e khanna marang-rang a oache ea ka hare, phetoho ea karolo e lumellanang ea marang-rang eo e etsahala. • Haeba o kgetha faele ya lvds mokhoa, kamano e tšoanang ea data le oache ea nako ea li-pins ho ngoliso ea ka hare ea SERDES e bolokiloe. Mokhoa ona o lefella tieho ea netweke ea lioache tsa LVDS, le lipakeng tsa phini ea data le phini ea oache ho litseleng tsa ngoliso ea SERDES.
Palo ea Lioache	1–9	E hlalosa palo ea lioache tse hlokahalang bakeng sa sesebelisoa ka seng moralong oa PLL. Litlhophiso tse kopiloeng bakeng sa maqhubu a tlhahiso, phetoho ea mohato, le potoloho ea mosebetsi li bontšoa ho latela palo ea lioache tse khethiloeng.
Hlalosa Maqhubu a VCO	Bulela kapa Tima	E u lumella ho fokotsa maqhubu a VCO ho boleng bo boletsoeng. Sena se na le thuso ha u theha PLL bakeng sa mokhoa oa kantle oa LVDS, kapa haeba ho batloa boholo bo itseng ba mohato oa mohato oa phetoho.
e tsoela pele…

Paramethara	Boleng ba Molao	Tlhaloso
Maqhubu a VCO (1)	—	• Neng Numella liparamente tsa oache ea tlhahiso ea 'mele e buletsoe- e bonts'a maqhubu a VCO a ipapisitseng le boleng ba Reference Clock Frequency, Multiply Factor (M-Counter), le Arola Factor (N-Counter). • Neng Numella liparamente tsa oache ea tlhahiso ea 'mele e timiloe- e u lumella ho bolela boleng bo kopiloeng bakeng sa maqhubu a VCO. Boleng ba kamehla ke 600.0 MHz.
Fana ka lebitso la lefatše la oache	Bulela kapa Tima	E o lumella ho reha lebitso la oache ea tlhahiso.
Lebitso la Tshupanako	—	Lebitso la oache ea mosebelisi ea Synopsis Design Constraints (SDC).
Maqhubu a Lakatsehang	—	E totobatsa maqhubu a oache ea sephetho sa kou ea oache e tsamaellanang, outclk[], ka MHz. Boleng ba kamehla ke 100.0 MHz. Bonyane le boholo ba boleng bo itšetlehile ka sesebelisoa se sebelisitsoeng. PLL e bala lipalo feela libakeng tse tšeletseng tsa pele tsa decimal.
Maqhubu a Sebele	—	E o lumella ho khetha maqhubu a oache ea 'nete ho tsoa lethathamong la maqhubu a fihlellehang. Boleng ba kamehla ke lebelo le haufi le fihlellehang ho frequency e batloang.
Diyuniti tsa Phase Shift	ps or likhato	E totobatsa yuniti ea shift shift bakeng sa kou e tsamaellanang ea oache, outclk[], ka picoseconds (ps) kapa likhato.
Lakatsehang Phase Shift	—	E totobatsa boleng bo kopiloeng bakeng sa phetoho ea mohato. Boleng ba kamehla ke 0 lipes.
Haele hantle Phase Shift	—	E u lumella ho khetha phetoho ea mokhahlelo oa 'nete ho tsoa lethathamong la litekanyetso tse ka fihlellehang. Boleng ba kamehla ke phetoho e haufi ka ho fetisisa e ka finyelloang ho ea mohatong o lakatsehang.
Lakatsehang Duty Cycle	0.0–100.0	E totobatsa boleng bo kopiloeng bakeng sa nako ea mosebetsi. Boleng ba kamehla ke 50.0%.
Mosebetsi oa Sebele	—	E u lumella ho khetha saekele ea 'nete ea mosebetsi ho tsoa lethathamong la boleng bo ka finyelloang. Boleng ba kamehla ke sekhechana sa mosebetsi se haufi ka ho fetisisa se fihlellehang ho saekele e lakatsehang ea mosebetsi.
Multiply Factor (M-Counter) (2)	4–511	E totobatsa ntlha ea ho atisa M-counter. Lenane la molao la k'hamphani ea M ke 4-511. Leha ho le joalo, lithibelo holim'a maqhubu a tlase a molao a PFD le maqhubu a phahameng a molao a VCO a beha moeli o sebetsang oa M ho 4-160.
Arola Factor (N-Counter) (2)	1–511	E bolela karohano ea N-counter. Lenane la molao la khaontara ea N ke 1–511. Leha ho le joalo, lithibelo ho sekhahla se tlase sa molao sa PFD se thibela mofuta o sebetsang oa khaontara ea N ho 1-80.
Arola Factor (C-Counter) (2)	1–511	E bolela karohano bakeng sa oache ea tlhahiso (C-counter).

1. Paramethara ena e fumaneha feela ha Enable physical output parameters e timiloe.
2. Paramethara ena e fumaneha feela ha Enable physical output parameters e butswe.

IOPLL IP Core Parameters - Settings Tab

Letlapa la 2. IOPLL IP Core Parameters - Settings Tab

Paramethara	Boleng ba Molao	Tlhaloso
PLL Bandwidth Preset	Tlase, Mahareng, kapa Phahameng	E totobatsa litlhophiso tsa PLL bandwidth preset. Khetho ea kamehla ke Tlase.
PLL Auto Reset	Bulela kapa Tima	Iketsetse PLL ka bowena ka ho lahleheloa ke senotlolo.
Etsa tlhahiso ea bobeli ea clk 'refclk1'	Bulela kapa Tima	Bulela ho fana ka oache ea ho boloka e hokeletsoeng ho PLL ea hau e ka fetohang ka oache ea hau ea mantlha ea litšupiso.
Bobeli Reference Clock Frequency	—	E khetha maqhubu a lets'oao la oache ea bobeli ea ho kenya. Boleng ba kamehla ke 100.0 MHz. Bonyane le boholo ba boleng bo itšetlehile ka sesebelisoa se sebelisitsoeng.
Etsa lets'oao la 'active_clk' ho bonts'a oache e kenang e ntseng e sebelisoa	Bulela kapa Tima	Bulela ho etsa tlhahiso ea activeclk. Sephetho sa activeclk se bonts'a oache ea ho kenya e sebelisoang ke PLL. Poelo e tlase e bonts'a refclk mme lets'oao le phahameng le bonts'a refclk1.
Theha lets'oao la 'clkbad' bakeng sa lioache tse kenang	Bulela kapa Tima	Bulela ho etsa liphetho tse peli tsa clkbad, e le 'ngoe bakeng sa oache e 'ngoe le e 'ngoe ea ho kenya. Lets'oao le tlase le bonts'a hore oache ea sebetsa 'me lets'oao le phahameng le bontša hore oache ha e sebetse.
Switchover Mode	Switchover e iketsang, Switchover ka Manual, kapa Automatic Switchover e nang le Manual Override	E totobatsa mokhoa oa switchover bakeng sa ts'ebeliso ea moralo. IP e tšehetsa mekhoa e meraro ea switchover: • Haeba o kgetha faele ya Switchover e iketsang mode, potoloho ea PLL e hlokomela oache e khethiloeng. Haeba oache e le 'ngoe e ema, potoloho e fetohela oacheng ea bekapo ka lipotoloho tse 'maloa ebe e nchafatsa matshwao a boemo, clkbad le activeclk. • Haeba o kgetha faele ya Switchover ka Manual mode, ha lets'oao la taolo, extswitch, le fetoha ho tloha holimo ho logic ho ea tlase, 'me le lula le le tlase bonyane lipotoloho tse tharo tsa oache, oache e kenang e fetohela ho e 'ngoe. Extswitch e ka hlahisoa ho tsoa ho FPGA logic core kapa pini ea ho kenya. • Haeba o kgetha Automatic Switchover e nang le Manual Override mode, ha lets'oao la extswitch le le tlase, le fetisa ts'ebetso ea switch othomathike. Ha feela extswitch e ntse e le tlase, ketso e 'ngoe ea switchover e thibetsoe. Ho khetha mokhoa ona, mehloli ea hau ea lioache tse peli e tlameha ho sebetsa 'me maqhubu a lioache tse peli a ke ke a fapana ka ho feta 20%. Haeba lioache ka bobeli li se ka lebelo le ts'oanang, empa phapang ea nako e ka hare ho 20%, sebaka sa ho lemoha tahlehelo ea oache se ka lemoha oache e lahlehileng. PLL e kanna ea theoha ka mor'a ho kenya oache ea PLL mme e hloka nako ea ho notlela hape.
Switchover Delay	0–7	E eketsa palo e itseng ea tieho ea potoloho ts'ebetsong ea switchover. Boleng ba kamehla ke 0.
Ho fihlella boema-kepe ba PLL LVDS_CLK/ LOADEN	E holofetse, Numella LVDS_CLK/ MOTLATSI 0, kapa Numella LVDS_CLK/ LAODA 0 & 1	Khetha Numella LVDS_CLK/LOADEN 0 or Numella LVDS_CLK/ LOADEN 0 & 1 ho thusa PLL lvds_clk kapa loaden port port. E nolofalletsa paramethara ena haeba PLL e fepa boloko ba LVDS SERDES ka PLL ea kantle. Ha u sebelisa li-port tsa I/O PLL tse nang le likou tsa LVDS, outclk[0..3] li sebelisetsoa lvds_clk[0,1] le loaden [0,1] likoung, outclk4 e ka sebelisoa bakeng sa likou tsa coreclk.
Numella phihlello ho boema-kepe ba PLL DPA	Bulela kapa Tima	Bulela ho nolofalletsa boema-kepe ba PLL DPA.
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Paramethara	Boleng ba Molao	Tlhaloso
Lumella monyetla oa ho fihlella port ea PLL ea kantle ea oache	Bulela kapa Tima	Bulela ho lumella boema-kepe ba PLL ba kantle ba ho ntša oache.
E hlalosa hore na ke outclk efe e tla sebelisoa e le mohloli oa extclk_out[0]	C0 – C8	E totobatsa outclk port e tla sebelisoa e le mohloli oa extclk_out[0].
E hlalosa hore na ke outclk efe e tla sebelisoa e le mohloli oa extclk_out[1]	C0 – C8	E totobatsa outclk port e tla sebelisoa e le mohloli oa extclk_out[1].

Cascading Tab

Letlapa la 3. IOPLL IP Core Parameters - Cascading Tab3

Paramethara	Boleng ba Molao	Tlhaloso
Theha lets'oao la 'cascade out' ho hokahanya le PLL e tlase	Bulela kapa Tima	Bulela ho theha cascade_out port, e bonts'ang hore PLL ena ke mohloli 'me e hokahana le sebaka (tlase) PLL.
E hlalosa hore na ke outclk efe e lokelang ho sebelisoa e le mohloli oa cascading	0–8	E totobatsa mohloli oa cascading.
Theha lets'oao la adjpllin kapa la cclk ho hokela le PLL e holimo	Bulela kapa Tima	Bulela ho theha boema-kepe ba ho kenya, bo bontšang hore PLL ena ke moo e eang teng 'me e hokahana le mohloli (ho ea holimo) PLL.

Letlapa la Phethahatso e Matla

Letlapa la 4. IOPLL IP Core Parameters - Matla a Reconfiguration Tab

Paramethara	Boleng ba Molao	Tlhaloso
Numella phetoho e matla ea PLL	Bulela kapa Tima	Bulela monyetla oa ho hlophisa bocha PLL ena (mmoho le PLL Reconfig Intel FPGA IP core).
Dumella phihlello ho maemakepe a dynamic phase shift	Bulela kapa Tima	Bulela sesebelisoa sa dynamic phase shift interface le PLL.
Khetho ea Moloko oa MIF (3)	Hlahisa MIF e ncha File, Kenya Configuration ho MIF e Teng File, le Etsa MIF File nakong ea Moloko oa IP	Kapa theha .mif e ncha file e nang le tlhophiso ya hajwale ya I/O PLL, kapa kenya tlhophiso ena ho .mif e teng file. U ka sebelisa sena .mif file nakong ea phetoho e matla ea ho lokisa I/O PLL ho litlhophiso tsa eona tsa hajoale.
Tsela ea ho MIF e Ncha file (4)	—	Kenya sebaka le file lebitso la e ncha .mif file ho boptjwa.
Tsela ea ho MIF e teng file (5)	—	Kenya sebaka le file lebitso la e teng .mif file u ikemiselitse ho eketsa ho.
e tsoela pele…

1. Paramethara ena e fumaneha feela ha Enable dynamic reconfiguration ea PLL e butswe.
2. Paramethara ena e fumaneha feela ha Hlahisa MIF e Ncha File e khethiloe e le MIF Generation
   Khetho.

   Paramethara	Boleng ba Molao	Tlhaloso
   Numella Dynamic Phase Shift bakeng sa Phallo ea MIF (3)	Bulela kapa Tima	Bulela ho boloka lisebelisoa tsa dynamic phase shift bakeng sa tokiso ea PLL.
   Khetho ea li-Counter tsa DPS (6)	C0–C8, Tsohle C, or M	E khetha k'haontara hore e kene ka har'a dynamic phase shift. M ke k'haonte ea maikutlo 'me C ke li-post-scale counters.
   Palo ea Liphetoho tse Matla (6)	1–7	E khetha palo ea li-phase shifting increments. Boholo ba sekhahla se le seng sa ho fetoha ha sekhahla se lekana le 1/8 ea nako ea VCO. Boleng ba kamehla ke 1.
   Dynamic Phase Shift Tataiso (6)	E ntle or E mpe	E khetha sebaka se feto-fetohang se tla bolokoa ho PLL MIF.

3. Paramethara ena e fumaneha feela ha Eketsa Tlhophiso ho MIF e Teng File e khethiloe e le Khetho ea Moloko oa MIF

IOPLL IP Core Parameters - Advanced Parameters Tab

Letlapa la 5. IOPLL IP Core Parameters - Advanced Parameters Tab

Paramethara	Boleng ba Molao	Tlhaloso
Mekhahlelo e tsoetseng pele	—	E bonts'a tafole ea litlhophiso tsa PLL tsa 'mele tse tla kengoa ts'ebetsong ho latela seo u se kentseng.

Tlhaloso ea Ts'ebetso

• I/O PLL ke sistimi e laolang maqhubu e hlahisang oache e hlahisoang ka ho ikamahanya le oache e kenang. PLL e bapisa phapang ea mohato lipakeng tsa lets'oao la ho kenya le lets'oao la phallo ea voltage-controlled oscillator (VCO) ebe e etsa synchronization ea mohato ho boloka sekhahla sa mohato o tsitsitseng (notlolo) ka makhetlo a mangata a ho kenya letsoho kapa pontšo ea boitsebiso. Khokahano kapa maikutlo a fosahetseng a sistimi e qobella PLL hore e notletsoe.
• U ka hlophisa li-PLL joalo ka li-multiplier, li-divider, li-demodulator, lijenereithara tsa ho latela, kapa li-circuits tsa ho khutlisa oache. U ka sebelisa li-PLL ho hlahisa maqhubu a tsitsitseng, ho khutlisa matšoao ho tsoa mocha oa puisano o lerata, kapa ho tsamaisa matšoao a oache ho pholletsa le moralo oa hau.

Mehaho ea kaho ea PLL

Li-block tsa I/O PLL ke mochini o bonang maqhubu a phase (PFD), pompo ea ho tjhaja, loop filter, VCO, le li-counter, joalo ka counter counter (M), pre-scale counter (N), le post- lisebelisoa tsa sekala (C). Mehaho ea PLL e ipapisitse le sesebelisoa seo u se sebelisang moralong oa hau.

Paramethara ena e fumaneha feela ha Nuble Dynamic Phase Shift bakeng sa Phallo ea MIF e buletsoe.

E Tloaelehileng I/O PLL Architecture

• Mantsoe a latelang a sebelisoa hangata ho hlalosa boitšoaro ba PLL:
  Nako ea senotlolo sa PLL — eo hape e tsejoang e le nako ea ho fumana PLL. Nako ea ho notlela ea PLL ke nako ea hore PLL e fihlele kamano ea sekhahla le sekhahla ka mor'a ho phahamisa matla, ka mor'a phetoho ea frequency ea tlhahiso, kapa ka mor'a hore PLL e tsosolose. Tlhokomeliso: Software ea simulation ha e fane ka mohlala oa nako ea senotlolo sa PLL. Ketsiso e bonts'a nako ea ho notlela ka lebelo le sa utloahaleng. Bakeng sa lintlha tsa 'nete tsa nako ea ho notlela, sheba lethathamo la lintlha tsa sesebelisoa.
• Qeto ea PLL - boleng bo tlase ba keketseho ea maqhubu a PLL VCO. Palo ea li-bits ho li-counter tsa M le N e khetholla boleng ba qeto ea PLL.
• PLL sample reiti-the FREF sampLining frequency e hlokahalang ho etsa phato le tokiso ea khafetsa ho PLL. Setšoantšo sa PLLample reiti ke fREF /N.

Senotlolo sa PLL

Senotlolo sa PLL se ipapisitse le matšoao a mabeli a kenyellelitsoeng mochining oa frequency detector. Letšoao la senotlolo ke tlhahiso e sa tloaelehang ea li-PLL. Palo ea lipotoloho tse hlokahalang ho kenya lets'oao la senotlolo li ipapisitse le oache e kenang ea PLL e koalang potoloho ea senotlolo. Arola boholo ba nako ea ho notlela ea PLL ka nako ea oache ea ho kenya PLL ho bala palo ea lipotoloho tsa oache tse hlokahalang ho kenya lets'oao la senotlolo.

Mekhoa ea ts'ebetso

IOPLL IP core e ts'ehetsa mekhoa e tšeletseng e fapaneng ea maikutlo a oache. Mokhoa o mong le o mong o lumella ho ikatisa le ho arola oache, ho fetoha ha mekhahlelo, le lenaneo la potoloho ea mosebetsi.

Lioache tse hlahisoang

• IOPLL IP ea mantlha e ka hlahisa matšoao a ho fihla ho a robong. Lipontšo tsa tlhahiso ea oache tse hlahisitsoeng li koala mokokotlo kapa li-blocks tse kantle ho mantlha.
• U ka sebelisa lets'oao la reset ho seta boleng ba oache e hlahisoang ho 0 le ho tima lioache tsa PLL.
• Oache e 'ngoe le e 'ngoe e hlahisoang e na le li-setting tse batloang moo u ka hlalosang boleng bo lakatsehang bakeng sa maqhubu a tlhahiso, phetoho ea mohato le potoloho ea mosebetsi. Li-setting tse lakatsehang ke li-setting tseo u batlang ho li sebelisa moralong oa hau.
• Litekanyetso tsa 'nete bakeng sa khafetsa, phetoho ea mohato, le potoloho ea mosebetsi ke litlhophiso tse haufi haholo (khakanyo e ntle ea litlhophiso tse lakatsehang) tse ka kengoang tšebetsong potolohong ea PLL.

Reference Clock Switchover

Sebopeho sa switch oache ea referense se lumella PLL ho chencha lipakeng tsa lioache tse peli tsa ho kenya litšupiso. Sebelisa tšobotsi ena bakeng sa ho fokotseha ha nako, kapa bakeng sa ts'ebeliso ea lioache tse peli joalo ka sistimi. Sistimi e ka bulela oache e sa sebetseng haeba oache ea mantlha e emisa ho sebetsa.
U sebelisa sesebelisoa sa switchover ea tšupa-nako, u ka bolela khafetsa hore na oache ea bobeli ke efe, ebe u khetha mokhoa le tieho bakeng sa switchover.

Sebono sa ho lahleheloa ke oache le block switchover ea oache e na le mesebetsi e latelang:

• E beha leihlo boemo ba oache ea litšupiso. Haeba tshupanako e hloleha, oache e fetohela mohloling oa ho kenya oache ea bekapo. Oache e nchafatsa boemo ba matšoao a clkbad le activeclk ho lemosa ketsahalo.
• E fetola oache ea litšupiso pele le morao lipakeng tsa maqhubu a mabeli a fapaneng. Sebelisa lets'oao la extswitch ho laola ketso ea switjha ka bowena. Kamora hore switchover e hlahe, PLL e kanna ea lahleheloa ke senotlolo ka nakoana mme ea feta ts'ebetsong ea ho bala.

PLL-to-PLL Cascading

Haeba u theola li-PLL ho moralo oa hau, mohloli (ho ea holimo) PLL e tlameha ho ba le maemo a tlase a marang-rang, athe sebaka sa PLL se tlamehang ho ba le maemo a holimo a marang-rang. Nakong ea cascading, tlhahiso ea mohloli oa PLL e sebetsa e le oache ea boitsebiso (kenyo) ea sebaka sa PLL. Litlhophiso tsa bandwidth tsa li-PLL tse senyehileng li tlameha ho fapana. Haeba litlhophiso tsa bandwidth tsa li-PLL tse cascade li tšoana, li-PLL tse cascade li ka ampphahamisa lerata ka maqhubu a itseng.Mohloli oa oache oa ho kenya adjpllin o sebelisoa bakeng sa ho phalla pakeng tsa fracturable fractional PLLs.

Boema-kepe

Letlapa la 6. IOPLL IP Core Ports

Paramethara	Mofuta	Boemo	Tlhaloso
refclk	Kenyeletso	Ho hlokahala	Mohloli oa oache o tsamaisang I/O PLL.
pele	Kenyeletso	Ho hlokahala	The asynchronous reset port bakeng sa lioache tse hlahisoang. Khanna boema-kepe bona holimo ho seta lioache tsohle tsa tlhahiso ho boleng ba 0. U tlameha ho hokela boema-kepe bona ho lets'oao la taolo ea mosebelisi.
fbclk	Kenyeletso	Taba ea boikhethelo	Sebaka sa ho kenya maikutlo sa kantle bakeng sa I/O PLL. IOPLL IP core e theha boema-kepe bona ha I/O PLL e sebetsa ka mokhoa oa ho fana ka maikutlo a kantle kapa mokhoa oa buffer oa ho lieha. Ho phethela loop ea maikutlo, khokahanyo ea boemo ba boto e tlameha ho hokahanya boema-kepe ba fbclk le boema-kepe ba kantle ba oache ea I/O PLL.
fboutclk	Sephetho	Taba ea boikhethelo	Boema-kepe bo fepang fbclk port ka potoloho ea mimic. Boema-kepe ba fboutclk bo fumaneha feela haeba I/O PLL e le maemong a kantle a maikutlo.
zdbfbclk	Ho iketsetsa liqeto	Taba ea boikhethelo	Boema-kepe ba mahlakore a mabeli bo hokahantsoeng le potoloho e etsisang. Boema-kepe bona bo tlameha ho hokela ho phini ea mahlakore a mabeli e behiloeng holim'a pina e ntle e fanoeng ea tlhahiso ea maikutlo ea I/O PLL. Boema-kepe ba zdbfbclk bo fumaneha feela ha I/O PLL e le ka har'a mokhoa oa "buffer" oa "zero- delay". Ho qoba ho bonahatsa lets'oao ha u sebelisa mokhoa oa ho thibela ho lieha ho feta lefela, u se ke oa beha mesaletsa holim'a phini ea I/O ea bidirectional.
notletsoe	Sephetho	Taba ea boikhethelo	IOPLL IP core e khanna boema-kepe bona holimo ha PLL e fumana senotlolo. Boema-kepe bo lula bo le holimo ha feela IOPLL e notletsoe. I/O PLL e tiisa boema-kepe bo notletsoeng ha mekhahlelo le maqhubu a oache ea litšupiso le oache ea maikutlo e le
e tsoela pele…

Paramethara	Mofuta	Boemo	Tlhaloso
			e ts'oanang kapa ka har'a mamello ea potoloho ea senotlolo. Ha phapang pakeng tsa matšoao a mabeli a oache e feta mamello ea potoloho ea senotlolo, I / O PLL e lahleheloa ke senotlolo.
refclk1	Kenyeletso	Taba ea boikhethelo	Mohloli oa oache oa bobeli oa litšupiso o tsamaisang I/O PLL bakeng sa tšobotsi ea switchover ea oache.
extswitch	Kenyeletso	Taba ea boikhethelo	Etsa hore lets'oao la extswitch le be tlase (1'b0) bonyane linako tse 3 tsa lioache ho fetola oache ka bowena.
activeclk	Sephetho	Taba ea boikhethelo	Letšoao le hlahisang ho bontša hore na ke mohloli ofe oa oache ea litšupiso e sebelisoang ke I/O PLL.
clkbad	Sephetho	Taba ea boikhethelo	Letšoao la ho tsoa le bonts'ang boemo ba mohloli oa oache o motle kapa o mobe.
cascade_out	Sephetho	Taba ea boikhethelo	Letšoao la tlhahiso le fepelang ho I/O PLL e tlase.
adjpllin	Kenyeletso	Taba ea boikhethelo	Letšoao la ho kenya le fepa ho tsoa ho I/O PLL e holimo.
outclk_[]	Sephetho	Taba ea boikhethelo	Oache e hlahisoang ke I/O PLL.

IOPLL Intel FPGA IP Core User Guide Archives

Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP

IP Core Version	Bukana ea Mosebelisi
17.0	Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
16.1	Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
16.0	Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
15.0	Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide

Nalane ea Tokomane ea Tokomane bakeng sa Tataiso ea Mosebelisi ea IOPLL Intel FPGA IP Core

Tokomane Version	Intel Quartus® Prime Version	Liphetoho
2019.06.24	18.1	E ntlafalitse tlhaloso ea lisebelisoa tsa oache tse inehetseng ho E Tloaelehileng I/O PLL Architecture setšoantšo.
2019.01.03	18.1	• Ntjhafatswa Ho fihlella boema-kepe ba PLL LVDS_CLK/LOADEN paramethara ka har'a IOPLL IP Core Parameters - Settings Tab tafole. • E ntlafalitse tlhaloso ea boema-kepe ba zdbfbclk sebakeng sa IOPLL IP Core Ports tafole.
2018.09.28	18.1	• E lokisitse tlhaloso ea exswitch ho IOPLL IP Core Ports tafole. • Reha li-cores tse latelang tsa IP ho ea ka Intel rebranding: - Fetotse Altera IOPLL IP core ho IOPLL Intel FPGA IP ea mantlha. - E fetotsoe Altera PLL Reconfig IP ea mantlha ho PLL Reconfig Intel FPGA IP ea mantlha. - E fetotsoe Arria 10 FPLL IP core ho fPLL Intel Arria 10/Cyclone 10 FPGA IP core.

Letsatsi	Phetolelo	Liphetoho
Phuptjane 2017	2017.06.16	• Tšehetso e ekelitsoeng bakeng sa lisebelisoa tsa Intel Cyclone 10 GX. • E rehiloe bocha joalo ka Intel.
Tšitoe 2016	2016.12.05	E ntlafalitse tlhaloso ea boema-kepe ba pele ba IP core.
Phuptjane 2016	2016.06.23	• Li-Parameters tsa IP tse ntlafalitsoeng - Tafole ea Litlhophiso. - E ntlafalitse tlhaloso ea Manual Switchover le Automatic Switchover ka li-parameter tsa Manual Override. Lets'oao la taolo ea ho fetola oache le sebetsa le le tlase. - E ntlafalitse tlhaloso ea paramente ea Switchover Delay. • Libali tse hlalositsoeng tsa M le C bakeng sa paramethara ea Khetho ea Counter ea DPS ho IP Core Parameters - Tafole ea Dynamic Reconfiguration Tab. • Fetola lebitso la boema-kepe ho tloha ho clkswitch ho ea ho extswitch ho setšoantšo se Tlwaelehileng sa I/O PLL Architecture.
Motšeanong 2016	2016.05.02	Li-Parameters tsa IP tse ntlafalitsoeng - Tafole ea Matla a Reconfiguration Tab.
Motšeanong 2015	2015.05.04	E ntlafalitse tlhaloso ea Noble access to PLL LVDS_CLK/LOADEN output parameter in IP Core Parameters - Settings Tab table. E kentse khokahanyo ho Sebopeho sa Letšoao Pakeng tsa Altera IOPLL le Altera LVDS SERDES IP Cores tafole ho I / O le High Speed ​​I / O ho Arria 10 Devices khaolo.
Phato 2014	2014.08.18	Tokollo ea pele.

Litokomane / Lisebelisoa

Intel UG-01155 IOPLL FPGA IP Core [pdf] Bukana ea Mosebelisi UG-01155 IOPLL FPGA IP Core, UG-01155, IOPLL FPGA IP Core, FPGA IP Core

Litšupiso

• Bukana ea Mosebelisi