Intel Cyclone 10 Native FloatingPoint DSP FPGA IP
Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide
Ho etsa parametering Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP
Khetha li-parameter tse fapaneng ho theha motheo oa IP o loketseng moralo oa hau.
- Ho Intel® Quartus® Prime Pro Edition, theha projeke e ncha e shebileng sesebelisoa sa Intel Cyclone® 10 GX.
- Ho IP Catalogue, tobetsa Library ➤ DSP ➤ DSP ea Pele ➤ Intel Cyclone 10 GX Native Floating Point DSP.
Intel Cyclone 10 GX Native Floating-Point DSP IP Core IP parameter mohlophisi oa bula. - Ka lebokoseng la puisano la New IP Variation, kenya Lebitso la Motheo ebe o tobetsa OK.
- Tlas'a Parameters, khetha Template ea DSP le ea View u batla bakeng sa IP ea hau ea mantlha
- Sebakeng sa DSP Block View, fetola oache kapa seta bocha rejisetara e 'ngoe le e 'ngoe e sebetsang.
- Bakeng sa Multiply Add kapa Vector Mode 1, tobetsa ho Chain In multiplexer ho GUI ho khetha ho kenya letsoho ho tloha boema-kepeng ba Chainin kapa Ax port.
- Tobetsa letšoao la Adder ho GUI ho khetha ho eketsa kapa ho tlosa.
- Tobetsa ho Chain Out multiplexer ho GUI ho nolofalletsa boema-kepe ba chainout.
- Tobetsa Hlahisa HDL.
- Tobetsa Qetella.
Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Parameters
Letlapa la 1. Mekhahlelo
| Paramethara | Boleng | Boleng ba kamehla | Tlhaloso |
| Setšoantšo sa DSP | Atisa Eketsa
Eketsa ka makhetlo a mangata Bokella Mokhoa oa 1 oa Vector XNUMX Mokhoa oa Vector 2 |
Atisa | Khetha mokhoa o lakatsehang oa ts'ebetso bakeng sa block ea DSP.
Tshebetso e kgethilweng e bonahala ho Thibelo ea DSP View. |
| View | Ngoliso e nolofalletsa ho Hlakola Ngoliso | Ngoliso e nolofalletsa | Likhetho tsa ho khetha sekema sa ho ts'oara kapa ho seta sekema bocha bakeng sa lirejistara view. Tshebetso e kgethilweng e bonahala ho Thibelo ea DSP View. |
| e tsoela pele… | |||
| Paramethara | Boleng | Boleng ba kamehla | Tlhaloso |
| Khetha Ngoliso e nolofalletsa bakeng sa Thibelo ea DSP View ho bonts'a sekema sa tshupanako sa rejisetara. U ka fetola lioache bakeng sa ngoliso e 'ngoe le e 'ngoe ho sena view.
Khetha Ngoliso e Hlakola bakeng sa Thibelo ea DSP View ho bonts'a leano la ho seta bocha. Bulela Sebelisa Mokhoa o le Mong o Hlakileng ho fetola sekema sa resets resets. |
|||
| Sebelisa Mokhoa o le Mong o Hlakileng | Ka kapa ho tima | E tima | Bulela paramethara ena haeba u batla ho seta bocha ha 'ngoe feela ho seta lirejisete tsohle tse ka har'a boloko ba DSP. Koala paramethara ena ho sebelisa likou tse fapaneng tsa ho seta bocha ho seta lirejistara bocha.
Bulela ho hlakisa 0 ho rejisetara ea tlhahiso; tima bakeng sa hlakileng 1 ho rejisetara ea tlhahiso. Hlakola 0 bakeng sa lirejistara tsa ho kenya li sebelisa aclr[0] sesupo. Hlakola 1 bakeng sa tšebeliso ea lihlahisoa le lipeipi aclr[1] lets'oao. Lirekoto tsohle tsa ho kenya li sebelisa letšoao la ho seta bocha aclr[0]. Lirekoto tsohle tsa tlhahiso le lipeipi li sebelisa letšoao la ho seta bocha aclr[1]. |
| DSP View Thibela. | |||
| Chain In Multiplexer (14) | Numella ho thibela | Thibela | Tobetsa ho multiplexer ho nolofalletsa ketane
boemakepe. |
| Chain Out Multiplexer (12) | Thibela Lumella | Thibela | Tobetsa ho multiplexer ho thusa ketane
boemakepe. |
| Adder (13) | +
– |
+ | Tobetsa ho Adder letshwao ho kgetha mokgwa wa tlatsetso kapa wa ho ntsha. |
| Ngolisa oache
• ax_clock (2) • ay_clock (3) • az_clock (4) • mult_pipeline_clock k(5) • ax_chainin_pl_clock k (7) • adder_input_clock (9) • adder_input_2_clock ck (10) • output_clock (11) • accumula_clock (1) • accum_pipeline_cl ock (6) • accum_adder_clock k (8) |
Ha ho letho Oache ea bo0
Oache ea bo1 Oache ea bo2 |
Oache ea bo0 | Ho qoba rejisetara efe kapa efe, fetolela oache ea registara ho Ha ho letho.
Fetolela oache ea ngoliso ho: • Oache ea bo0 ho sebelisa lets'oao la clk[0] joalo ka mohloli oa oache • Oache ea bo1 ho sebelisa lets'oao la clk[1] joalo ka mohloli oa oache • Oache ea bo2 ho sebelisa lets'oao la clk[2] joalo ka mohloli oa oache U ka fetola litlhophiso tsena feela ha u khetha Ngoliso e nolofalletsa in View paramethara. |
Setšoantšo sa 1. DSP Block View
Letlapa la 2. DSP Templates
| Litšoantšo tsa DSP | Tlhaloso |
| Atisa | E etsa ts'ebetso e le 'ngoe e nepahetseng ea ho atisa 'me e sebelisa equation e latelang:
• Tsoa = Ay * Az |
| Eketsa | E etsa ts'ebetso e le 'ngoe e nepahetseng ea ho eketsa kapa ea ho tlosa 'me e sebelisa lipalo tse latelang:.
• Tsoa = Ay + Selepe • Tsoa = Ay – Selepe |
| Eketsa | Mokhoa ona o etsa katiso e nepahetseng e le 'ngoe, e lateloang ke ho eketsa kapa ho tlosa, ebe o sebelisa lipalo tse latelang.
• Tsoa = (Ay * Az) – ketane • Tsoa = (Ay * Az) + ketane • Tsoa = (Ay * Az) – Selepe • Tsoa = (Ay * Az) + Selepe |
| Ikatise Bokella | E etsa katoloso ea lintlha tse phaphametseng e lateloang ke ho eketsa kapa ho tlosa lintlha tse phaphametseng ka sephetho sa pejana sa ho atisa 'me se sebelisa lipalo tse latelang:
• Tsoa(t) = [Ay(t) * Az(t)] – Tsoa (t-1) ha li bokellana sesupo se khannoa holimo. • Tsoa (t) = [Ay(t) * Az(t)] + Tsoa (t-1) ha boema-kepe bo bokelletsoeng bo phahamisetsoa holimo. • Out(t) = Ay(t) * Az(t) ha accumulate port e khannoa tlase. |
| Mokhoa oa Vector 1 | E etsa katoloso ea ntlha e phaphametseng e lateloang ke tlatsetso kapa ho tlosa lintlha tse phaphametseng ka ketane ea ketane ho tsoa ho block ea DSP e fapaneng mme e sebelisa li-equations tse latelang:. |
| e tsoela pele… | |
| Litšoantšo tsa DSP | Tlhaloso |
| • Tsoa = (Ay * Az) – ketane
• Tsoa = (Ay * Az) + ketane • Tsoa = (Ay * Az) , ketane = Selepe |
|
| Mokhoa oa Vector 2 | E etsa katiso ea lintlha tse phaphametseng moo IP core e fepang sephetho sa katiso e le ketane ka kotloloho. Mokotla oa IP ebe o eketsa kapa o tlosa ketane ea ketane ho tloha ho thibela e fetileng ea DSP ho tloha ho kenya Ax e le sephetho sa tlhahiso.
Mokhoa ona o sebelisa li-equations tse latelang: • Tsoa = Selepe – ketane , ketane = Ay * Az • Ho tsoa = Selepe + ketane , ketane = Ay * Az • Ho tsoa = Selepe , ketane = Ay * Az |
Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Signals
Setšoantšo sa 2. Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Signals
Palo e bonts'a matšoao a ho kenya le ho tsoa a mantlha a IP.
Letlapa la 3. Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Input Signals
| Lebitso la Letshwao | Mofuta | Bophara | Ea kamehla | Tlhaloso |
| selepe[31:0] | Kenyeletso | 32 | Tlase | Kenya bese ya data ho morekisi. E fumaneha ka:
• Eketsa mokgwa • Multiply-Add mode ntle le ketane le chainout tšobotsi • Mokhoa oa 1 oa Vector • Mokhoa oa 2 oa Vector |
| ee[31:0] | Kenyeletso | 32 | Tlase | Kenya bese ya data ho morekisi.
E fumaneha ka mekhoa eohle ea ts'ebetso ea sebaka se phaphametseng. |
| tse[31:0] | Kenyeletso | 32 | Tlase | Kenya bese ya data ho morekisi. E fumaneha ka:
• Atisa • atisa Eketsa • Ikatisetsa • Mokhoa oa 1 oa Vector • Mokhoa oa 2 oa Vector |
| ketane[31:0] | Kenyeletso | 32 | Tlase | Hokela mats'oao ana ho mats'oao a ketane ho tsoa setsing se fetileng sa DSP IP se phaphametseng. |
| klk[2:0] | Kenyeletso | 3 | Tlase | Kenya matšoao a oache bakeng sa lirekoto tsohle.
Matshwao ana a ditshupanako a fumaneha feela ha e le efe ya direjistara tse kenyang, diphaephe, kapa rejisetara ya tlhahiso e behilwe ho Oache0 or Oache1 or Oache2. |
| ena[2:0] | Kenyeletso | 3 | Phahameng | Oache e nolofalletsa clk[2:0]. Matshwao ana a sebetsa-Hodimo.
• ena[0] ke bakeng sa Oache0 • ena[1] ke bakeng sa Oache1 • ena[2] ke bakeng sa Oache2 |
| aklr[1:0] | Kenyeletso | 2 | Tlase | Lipontšo tse hlakileng tsa Asynchronous bakeng sa lirekoto tsohle. Matshwao ana a sebetsa-hodimo.
Sebelisa aclr[0] bakeng sa lirejisete tsohle tsa ho kenya le ho sebelisa aclr[1] bakeng sa lipeipi tsohle le li-registe tsa tlhahiso. |
| bokella | Kenyeletso | 1 | Tlase | Letšoao la ho kenya ho lumella kapa ho tima tšobotsi ea accumulator.
• Etsa lets'oao lena ho etsa hore maikutlo a ntlafatse tlhahiso ea adder. • Tlosa letšoao lena ho tima mochine oa maikutlo. O ka tiisa kapa oa hlakola lets'oao lena nakong ea ts'ebetso. E fumaneha ka mokhoa oa Multiply Accumulate. |
| ketane [31:0] | Sephetho | 32 | — | Hokela matshwao ana ho matshwao a ketane a ntlha e latelang ya DSP IP ya mantlha e phaphametseng. |
| sephetho[31:0] | Sephetho | 32 | — | Sephetho sa bese ea data ho tsoa ho IP core. |
Nalane ea Phetoho ea Litokomane
Liphetoho ho Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP User Guide
| Letsatsi | Phetolelo | Liphetoho |
| La 2017 Pulungoana XNUMX | 2017.11.06 | Tokollo ea pele. |
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
Litokomane / Lisebelisoa
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Intel Cyclone 10 Native FloatingPoint DSP FPGA IP [pdf] Bukana ea Mosebelisi Cyclone 10 Native FloatingPoint DSP FPGA IP, 10 Native FloatingPoint DSP FPGA IP, Native FloatingPoint DSP FPGA IP, FloatingPoint DSP FPGA IP, DSP FPGA IP, FPGA IP |
