PolarFire® FPGA Production
Selelekela
The PolarFire® MPF050T, MPF100T, MPF200T, MPF300T, and MPF500T production FPGA devices are subject to the limitations described in this document. This document describes updates about known issues, available limitations, and workarounds. It provides a snapshot of the current validation status for feature sets. The document highlights dependencies that may exist between silicon device revisions and specific support by Libero® SoC software versions. Contact Tšehetso ea Theknoloji ea Microchip bakeng sa lintlha tse ling.
Letlapa la 1. Liphetoho tsa lisebelisoa
| Sesebelisoa | Sephutheloana | Liphetoho |
| MPF050T, TL, TS, TLS, TC | FCSG325 and FCVG484 | 0, 1 |
| MPF100T, TL, TS, TLS, TC | FCG484, FCVG484, and FCSG325 | 0, 1, 2 |
| MPF200T, TL, TS, TLS, TC | FCG784, FCG484, FCVG484, FCSG536, and FCSG325 | 0, 1, 2 |
| MPF300T, TL, TS, TLS, TC | FCG1152, FCG784, FCG484, FCVG484, and FCSG536 | 0, 1, 2 |
| MPF500T, TL, TS, TLS, TC | FCG1152 and FCG784 | 0, 1 |
Hlokomela: Bona CN19014 for details on revision 1 devices.
Letlapa la 2. Likhetho tsa lisebelisoa
| Sesebelisoa | Extended Commercial 0 °C–100 °C | Industrial –40 °C–100 °C | STD | –1 | Transceivers T | Lower Static Power L | Data Security S |
| MPF050T, MPF100T, MPF200T, MPF300T, MPF500T | Ee | Ee | Ee | Ee | Ee | - | - |
| MPF050TL, MPF100TL, MPF200TL, MPF300TL, MPF500TL | Ee | Ee | Ee | - | Ee | Ee | - |
| MPF050TS, MPF100TS, MPF200TS, MPF300TS, MPF500TS | - | Ee | Ee | Ee | Ee | - | Ee |
| MPF050TLS, MPF100TLS, MPF200TLS, MPF300TLS, MPF500TLS | - | Ee | Ee | - | Ee | Ee | Ee |
| MPF050TC, MPF100TC, MPF200TC, MPF300TC, MPF500TC | Ee | Ee | Ee | - | Che | - | - |
For specifications, see PolarFire FPGA Datasheet.
Litlhaloso tsa Errata le Workaround
Likarolo tse latelang li hlalosa liphoso tsa sesebelisoa le li-workaround hohle moo ho hlokahalang. Tokomane ena e reretsoe ho hlalosa ho fapana kapa ho kheloha tlhahisoleseling ho PolarFire FPGA Datasheet kapa mosebelisi ofe kapa ofe oa PolarFire kapa tataiso ea demo.
The following table lists the specific device errata and the affected PolarFire production devices.
Lethathamo la 1-1. Kakaretso ea PolarFire FPGA Errata
| Tlhaloso | MPF050T, TL, TS, TLS, TC | MPF100T, TL, TS, TLS, TC | MPF200T, TL, TS, TLS, TC | MPF300T, TL, TS, TLS, TC | MPF500T, TL, TS, TLS, TC |
| MPF300T-ES bitstream compatibility | N/A | N/A | N/A | * | N/A |
| System controller suspend mode interaction with JTAG | * | * | * | * | * |
| PCIe SECDED ECC reporting counters and interrupts | * | * | * | * | * |
| External VERIFY_DIGEST with POR Digest Check for Fabric Components | * | * | * | * | * |
* indicates that the errata exists for that particular device. Details are discussed in the following
likarolo.
For feature clarifications about supported transceiver protocols, see the section Supported Transceiver Protocol Status for Production Devices.
1.1. Bitstream Compatibility
Li-bitstreams tsa MPF300T-ES li ke ke tsa sebelisoa ho hlophisa lisebelisoa tsa pele ho tlhahiso (PP) kapa lisebelisoa tsa MPF300T tsa tlhahiso.
1.2. System Controller Suspend Mode Interaction with JTAG
If the system controller’s suspend mode is enabled, device initialization may be interrupted after exiting JTAG programming. As a workaround, reset the device after JTAG mananeo.
1.3. PCIe® SECDED Reporting Defeatured
When ECC is enabled (default) within the PCIe hard IP block, the single error correction and double error detection error reporting counters and interrupt registers show erroneous values.
The following features of the PCIe SECDED are being defeatured:
- Single error correction reporting features
- Double error detection feature
More information about this is available in the change impact analysis document.
1.4. Deprecated Feature: Use of External VERIFY_DIGEST with POR Digest Check for Fabric Components
Ha sesebelisoa se hlophisitsoe bakeng sa tlhahlobo ea "Fabric Power-On-Reset" (POR), VERIFY_DIGEST ea likarolo tsa lesela ka J.TAG/SPI e ka tlaleha liphoso tsa bohata 'me ea theoha. Taba ena ha e ame:
- VERIFY_DIGEST of non-fabric components
- CHECK_DIGEST via system service call
- VERIFY_DIGEST functionality for fabric components when Fabric POR digest check is disabled
For more information, refer to the latest revision of the PolarFire Family FPGA Security User Guide.
Boemo ba Protocol ea Transceiver bakeng sa Lisebelisoa tsa Tlhahiso
Bokhoni ba protocol ea Transceiver bo netefalitsoe le ho lekoa bakeng sa ho tiea ho latela litlhaloso tse thathamisitsoeng ho PolarFire FPGA Datasheet le PolarFire Family Transceiver User Guide.
The following table summarizes transceiver protocols and validation status for production devices.
This table does not apply to PolarFire core devices (MPFxxxTC).
Lethathamo la 2-1. Li-Protocol tsa Transceiver tse tšehelitsoeng
| Transceiver Protocol by Device | MPF050T/MPF100T/ MPF200T/MPF300T/ MPF500T Status |
Lintlha |
| SGMII/1000BASE-X | Feletseng | Transceiver: 1.25 Gbps with CoreTSE IP core. TxPLL SyncE validation is in progress. Contact the factory. |
| CPRI | Feletseng | Support for CPRI data rates 1–7 and 7A, 8, 9. |
| 10GBASE-R | Feletseng | Transceiver: 10.3125 Gbps with Core10GMAC IP core. TxPLL SyncE is supported. IEEE® 1588 time stamping ha e tšehetsoe. |
| 10GBASE-KR | Feletseng | Contact Microchip for a complete solution. |
| Interlaken | Feletseng | - |
| JESD204B | Feletseng | Up to 12.5G with CoreJESD20BTX/RX IP core. |
| PCIE Endpoint Gen1/Gen2 | Feletseng | - |
| PCIE Rootport Gen1/Gen2 | Feletseng | - |
| LiteFast | Feletseng | Up to 12.7 Gbps (8b10b only). |
| XAUI | Feletseng | - |
| RXAUI | Feletseng | - |
| HiGig/HiGig+ | Feletseng | - |
| Boema-kepe | Feletseng | Per VESA DisplayPort Standard 1.2a. |
| SRIO | Feletseng | - |
| PMA only | Feletseng | - |
| SATA | Feletseng | Ikopanye le feme. |
| Fiber channel | Feletseng | Tested for electrical compliance. |
| SDI | Feletseng | HD-SDI (1.485 Gbps) and 3G-SDI (2.970 Gbps) are supported. SD-SDI (270 Mbps) is supported. 6G-SDI and 12G-SDI are supported. |
| OTN | Feletseng | Tested for electrical compliance. |
| QSGMII | Feletseng | - |
| USXGMII | Feletseng | - |
| CoaXPress | Feletseng | Tested with external PHY. |
| SLVS-EC | Feletseng | - |
| Half-duplex (independent Rx/Tx) | Feletseng | - |
Nalane ea Phetoho
Nalane ea ntlafatso e hlalosa liphetoho tse kentsoeng tšebetsong tokomaneng. Liphetoho
li thathamisitsoe ka ntlafatso, ho qala ka khatiso ea morao-rao.
| Khatiso | Letsatsi | Tlhaloso |
| B | 08/2025 | • Added MPF050T and TC information throughout the document. • E ntlafalitsoe Letlapa la 1. Liphetoho tsa lisebelisoa. • Deprecated Feature: Use of External VERIFY_DIGEST with POR Digest Check for Fabric Likaroloana. • Noted that Lethathamo la 2-1. Li-Protocol tsa Transceiver tse tšehelitsoeng does not apply to PolarFire core devices (MPFxxxTC). |
| A | 01/2024 | • Defeatured PCIe SECDED reporting. More information about this is available in the change impact analysis document. • Added references to MPF050T in Kakaretso ea Errata le Supported Transceiver Protocols. • Updated to Microchip template. • Updated document number from ER0218 to DS80001111. |
| 6.0 | 05/2021 | • Updated details for SGMII/1000BASE-X row in Table 4 Supported Transceiver Protocols. |
| 5.0 | 12/2020 | • Removed information for “Dynamic Training of HSIO/GPIO IOD Interfaces” and “Temperature-Voltage Sensor (TVS) Litekanyetso tsa Mocheso oa Lifolakha". • Updated status for SDI, SLVS-EC, and Half-duplex (independent Rx/Tx) to “Complete”. • “SD-SDI (270 Mbps)” and “6G-SDI and 12G-SDI” are supported. • Deleted “Enhanced Receiver Management (ERM) is not supported”. |
| 4.0 | 12/2019 | • Removed MIPI D-PHY support information. For MIPI D-PHY support information, see the PolarFire Datasheet Revision 1.7. • Added Temperature-VoltagTlhahisoleseling ea e Sensor (TVS) (ho ea ka CN19030). • Added system control suspend mode interaction with JTAG. |
| 3.0 | 09/2019 | • Removed memory interface limitation from errata for production silicon using Libero SoC version 12.0 or later software. • Removed IOCDR limitations from errata for production silicon using Libero SoC version 12.1 or later software. • Removed RxPLL behavior and DFE calibration limitations from errata for production silicon using Libero SoC version 12.1 or later software using PF_XCVR_ERM core. • Removed errata on the IBIS-AMI DFE support. The released IBIS-AMI models offer full feature support. |
| 2.0 | 11/2018 | • MPF100T device offerings were added. |
| 1.0 | 11/2018 | • It was the first publication of this document, including the MPF200T and MPF300T device offerings. |
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