Litaelo tsa ho falla ha intel ho tloha Arria 10 ho ea Stratix 10 bakeng sa 10G Ethernet Subsystem
Litaelo tsa ho falla ho tloha Intel® Arria® 10 ho ea Intel® Stratix® 10 bakeng sa 10G Ethernet Subsystem
The Low Latency (LL) Ethernet 10G (10GbE) Media Access Controller (MAC) Intel® FPGA IP core e kenyelletsa Intel Stratix® 10 le Intel Arria® 10 design examptse tsamaellanang le lintlha tsa IEEE 802.3-2008. Likamano pakeng tsa Intel Stratix 10 LL 10GbE MAC Intel FPGA IP core le sebopeho sa 'mele (PHY) IP core li fapane ha li bapisoa le Intel Arria 10 LL 10GbE MAC Intel FPGA IP core le PHY IP core.
Litaelo tsena tsa ho falla li etselitsoe ba tloaelaneng le Intel Arria 10 LL 10GbE MAC Intel FPGA IP core. Sebelisa litataiso tsena tsa ho falla haeba u batla ho falla moralo oa hau oa Intel Arria 10 LL 10GbE MAC ho sebelisa lisebelisoa tsa Intel Stratix 10.
Intel Stratix 10 LL 10GbE MAC System
Papiso lipakeng tsa Intel Stratix 10 le Intel Arria 10 Design Examples bakeng sa LL 10GbE MAC Intel FPGA IP Core
| Moqapi Example | Mefuta e fapaneng ea MAC | PHY | Ntlafatso Kit | Intel Arria 10 | Intel Stratix 10 |
| 10GBASE-R
Ethernet |
10G | Native PHY (Ts'ehetso ea L/H-tile Native PHY bakeng sa Intel Stratix 10) | Intel Arria 10/ Intel Stratix 10 GX Transceiver Signal Botšepehi | Ee | Ee |
| 1G/2.5G Ethernet e nang le 1588 | 1G/2.5G | 1G/2.5G/5G/10G
Multi-rate Ethernet PHY |
Intel Arria 10/ Intel Stratix 10 GX Transceiver Signal Botšepehi | Ee | Ee |
| 1G/2.5G/10G
Ethernet |
1G/2.5G/10G | 1G/2.5G/5G/10G
Multi-rate Ethernet PHY |
Intel Arria 10/ Intel Stratix 10 GX Transceiver Signal Botšepehi | Ee | Ee |
| 10GBASE-R
Ngolisa Mokhoa oa Ethernet |
10G | Native PHY | Intel Arria 10 GX Transceiver Signal Botšepehi | Ee | Ha e fumanehe |
| XAUI Ethernet | 10G | XAUI PHY | Intel Arria 10 GX FPGA | Ee | Ha e fumanehe |
| 1G/10G Ethernet | 1G/10G | 1G/10GbE le 10GBASE-KR PHY | Intel Arria 10 GX Transceiver Signal Botšepehi | Ee | Ha e fumanehe |
| tsoela pele. | |||||
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.
Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
| Moqapi Example | Mefuta e fapaneng ea MAC | PHY | Ntlafatso Kit | Intel Arria 10 | Intel Stratix 10 |
| 1G/10G Ethernet e nang le 1588 | 1G/10G | 1G/10GbE le 10GBASE-KR PHY | Intel Arria 10 GX Transceiver Signal Botšepehi | Ee | Ha e fumanehe |
| 10M /
100M/1G/10G Ethernet |
10M /
100M/1G/10G |
1G/10GbE le 10GBASE-KR PHY | Intel Arria 10 GX Transceiver Signal Botšepehi | Ee | Ha e fumanehe |
| 10M /
100M/1G/10G Ethernet e nang le 1588 |
10M /
100M/1G/10G |
1G/10GbE le 10GBASE-KR PHY | Intel Arria 10 GX Transceiver Signal Botšepehi | Ee | Ha e fumanehe |
| 1G/2.5G Ethernet | 1G/2.5G | 1G/2.5G/5G/10G
Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver Signal Botšepehi | Ee | Ha e fumanehe |
| 10G USXGMII
Ethernet |
1G/2.5G/5G/10G (USXGMII) | 1G/2.5G/5G/10G
Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver Signal Botšepehi | Ee | Ha e fumanehe |
Hlokomela:
U ka fihlella lethathamo la moralo oa exampho feta ka mohlophisi oa paramethara ea LL 10GbE MAC ho software ea Intel Quartus® Prime Pro Edition.
Lintlha Tse Amanang
- Low Latency Ethernet 10G MAC User Guide
- Intel Stratix 10 Low Latency Ethernet 10G MAC Design Example Bukana ea Mosebelisi
- Intel Stratix 10 L- le H-Tile Transceiver PHY Bukana ea Mosebelisi
Litlhophiso tse tšehelitsoeng tsa Intel Stratix 10 le Intel Arria 10 LL 10GbE Meralo ea MAC
Tafole e latelang e thathamisa tsohle tse ka khonehang tsa Intel Stratix 10 le Intel Arria 10 Ethernet IP.
Litlhophiso tse tšehelitsoeng tsa Intel Arria 10 le Intel Stratix 10 Ethernet IP Configuration.
| IP Core | Intel Arria 10 | Intel Stratix 10 | |
| LL 10GbE MAC | Lebelo | • 10G | |
| • 1G/10G | |||
| • 10M/100M/1G/10G | |||
| • 1G/2.5G | |||
| • 1G/2.5G/10G | |||
| • 1G/2.5G/5G/10G (USXGMII interface) | |||
| • 10M/100M/1G/2.5G | |||
| • 10M/100M/1G/2.5G/10G | |||
| IEEE 1588v2 tšobotsi | • 10G | • 10G | |
| • 1G/10G | • 1G/10G | ||
| • 10M/100M/1G/10G | • 10M/100M/1G/10G | ||
| • 1G/2.5G | • 1G/2.5G | ||
| • 1G/2.5G/10G | |||
| tsoela pele. | |||
| IP Core | Intel Arria 10 | Intel Stratix 10 | |
| 1G/2.5G/5G/10G Multi-rate Ethernet PHY | Lebelo | • 2.5G
• 1G/2.5G • 1G/2.5G/10G (MGBASE-T PHY) • 1G/2.5G/5G/10G (USXGMII interface/NBASE-T PHY) |
|
| IEEE 1588v2 tšobotsi | • 2.5G
• 1G/2.5G |
• 2.5G
• 1G/2.5G • 1G/2.5G/10G Ha e sebetse bakeng sa mokhoa oa SGMII o lumelletsoeng. |
|
| Mokhoa oa SGMII | Ha e fumanehe | • 1G/2.5G
• 1G/2.5G/10G |
|
| XAUI PHY | E fumaneha | Ha e fumanehe | |
| Intel Stratix 10 L-tile/H-tile Transceiver Native PHY | Ha e fumanehe | Li-presets tse tšehetsoeng:
• 10GBASE-R • 10GBASE-R 1588 • 10GBASE-R Nako e Tlaase • 10GBASE-R ka KR FEC |
|
| Intel Arria 10 Transceiver Native PHY | Li-presets tse tšehetsoeng:
• 10GBASE-R • 10GBASE-R Mokhoa oa ho ngolisa • 10GBASE-R Nako e Tlaase • 10GBASE-R ka KR FEC |
Ha e fumanehe | |
| Intel Arria 10 1G/10GbE le 10GBASE-KR PHY | E fumaneha | Ha e fumanehe | |
| Intel Stratix 10 10GBASE-KR PHY | Ha e fumanehe | E fumaneha | |
Ho koala le ho seta botjha Infrastructure
Intel Stratix 10 LL 10GbE MAC le Intel Stratix 10 Transceiver Native PHY IP Cores
O ka lokisa Intel Stratix 10 Transceiver Native PHY IP core ho kenya ts'ebetsong 10GBASE-R PHY ka lesela le ikhethileng la Ethernet le sebetsang ka sekhahla sa data sa 10.3125 Gbps joalo ka ha se hlalositsoe ho Clause 49 ea IEEE 802.3-2008. Tlhophiso ena e fana ka XGMII ho LL 10GbE MAC Intel FPGA IP core mme e sebelisa mocha o le mong oa 10.3125Gbps PHY bakeng sa ho hokahana ka kotloloho le mojule o monyane oa sebopeho-factor pluggable plus (SFP+) o sebelisa sebopeho se senyenyane sa motlakase (SFI) tlhaloso.
Setšoantšo se latelang se bontša ho falla ho tloha ho moralo oa Intel Arria 10 ho ea ho moralo oa Intel Stratix 10.
Scheme ea ho koala le ho seta bocha bakeng sa LL 10GbE MAC le Intel Stratix 10 Transceiver Native PHY ka 10GBASE-R Design Ex.ample Interface
Lintlha Tse Amanang
AN795: Ho phethahatsa Litaelo bakeng sa 10G Ethernet Subsystem Ho Sebelisa Low Latency 10G MAC IP Core ho Arria 10 Devices
Intel Stratix 10 LL 10GbE MAC le Intel Stratix 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Cores
1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP core bakeng sa lisebelisoa tsa Intel Stratix 10 e fana ka GMII le XGMII ho LL 10GbE MAC Intel FPGA IP core. The 1G/ 2.5G/5G/10G Multi-rate Ethernet PHY IP core e sebelisa mocha o le mong 1G/ 2.5G/5G/10Gbps serial PHY. Moqapi o fana ka khokahanyo e tobileng ho li-module tsa 1G / 2.5GbE tse peli tsa lebelo la SFP + plugable, lisebelisoa tsa PHY tsa koporo tsa MGBASE-T, kapa li-interfaces tsa chip-to-chip. Li-cores tsena tsa IP li tšehetsa litefiso tsa data tse ka lokisoang bocha.
Setšoantšo se latelang se bontša ho falla ha Intel Arria 10 ho ea ho moralo oa Intel Stratix 10.
Scheme ea ho koala le ho seta bocha bakeng sa LL 10GbE MAC le 1G/2.5G/5G/10G Multi-rate Ethernet PHY Design Example (1G/2.5G/10G Mode) bakeng sa Intel Stratix 10 Devies
Palo e latelang e bonts'a moralo oa morao-rao oa ho ts'oara le ho seta bocha oa 1G/2.5G Ethernet e nang le sebopeho sa IEEE 1588v2 ex.ampe lebisitsoe ho lisebelisoa tsa Intel Stratix 10. Ho na le phapang lipakeng tsa tharollo ena le mofuta o hlahisitsoeng lisebelisoa tsa Intel Arria 10. Phetoho ea hlokahala ha ho falla moralo ho tloha lisebelisoa tsa Intel Arria 10 ho ea ho lisebelisoa tsa Intel Stratix 10.
Scheme ea ho koala le ho seta bocha bakeng sa LL 10GbE MAC le 1G/2.5G/5G/10G Multi-rate Ethernet PHY Design Example (1G/2.5G Mode e nang le IEEE 1588v2 Feature) bakeng sa Intel Stratix 10 Devices
Sebaka se secha sa ho kenya oache latency_sclk se fumaneha lisebelisoa tsa Intel Stratix 10. Boema-kepe bona boa fumaneha ha o bulela paramethara ea Numella li-port tsa ho lekanya ka morao ho Intel Stratix 10 L/H-Tile Transceiver Native PHY IP core kapa Enable IEEE 1588 Precision Time Protocol parameter ho 1G/2.5G/5G/10G Multi- sekhahla Ethernet PHY Intel FPGA IP konokono. Kou ena ea hlokahala bakeng sa mohlala oa deterministic latency methang bakeng sa lisebelisoa tsa Intel Stratix 10. Ho fumana lintlha tse ling, sheba khaolo ea Deterministic Latency Use Model ho Intel Stratix 10 L/H-Tile Transceiver PHY Bukana ea Mosebelisi.
Ho hokela I/O phase-locked loop (IOPLL), eketsa Intel Stratix 10 Clock Control (stratix10_clkctrl) IP ho tsoa ho IP Catalog. IOPLL e fana ka likarolo tse peliamplioache tse ling moetsong ona: 53.33 MHz bakeng sa 2.5G mode le 80 MHz bakeng sa 1G mode.
Setšoantšo se latelang se bontša lintlha tsa khokahanyo tse thehiloeng ho moralo oa 1G / 2.5G Ethernet.
Setšoantšo sa Khokahano bakeng sa 1G/2.5G Ethernet e nang le Moralo oa 1588 oa Intel Stratix 10 Devices
U tlameha ho etsa bonnete ba hore boema-kepe ba inclk0x bo hokahana le 2.5G sampling oache le boema-kepe ba inclk1x bo hokahana le 1G sampling oache. Boema-kepe ba oache ea tlhahiso ea taolo ea oache bo fetoha boema-kepe ba latency_sclk. Bakeng sa ho falla ha moralo ho tloha ho lisebelisoa tsa Intel Arria 10 ho ea ho lisebelisoa tsa Intel Stratix 10, u ka boela ua sebelisa khokahanyo e tšoanang pakeng tsa 1G / 2.5G reconfiguration block le transceiver reset controller.
Lintlha Tse Amanang
- Intel Stratix 10 L- le H-Tile Transceiver PHY Bukana ea Mosebelisi
- AN795: Litaelo tsa ho kenya ts'ebetsong bakeng sa 10G Ethernet Subsystem Ho sebelisa Low Latency 10G MAC IP Core ho Arria 10 Devices
- Intel Stratix 10 Clock le PLL User Guide
'Mapa oa Ngoliso ea IP
LL 10GbE MAC Intel FPGA IP ea mantlha bakeng sa lisebelisoa tsa Intel Stratix 10 e sebelisa 'mapa o tšoanang oa ngoliso joalo ka LL 10GbE MAC Intel FPGA IP core bakeng sa lisebelisoa tsa Intel Arria 10. Multi-rate Ethernet PHY le 10GBASE-R PHY presets le tsona li sebelisa 'mapa o tšoanang oa ngoliso bakeng sa meralo ea Intel Stratix 10 le Intel Arria 10. LL 10GbE MAC Intel FPGA IP ea mantlha bakeng sa lisebelisoa tsa Intel Stratix 10 e ntse e ts'ehetsa tšebelisano ea morao-rao le 10GbE IP e nang le adaptara ea 64-bit Avalon Memory-Mapped (MM).
Lintlha Tse Amanang
Low Latency Ethernet 10G MAC User Guide.
Phapang ea Khokahano ea Signal lipakeng tsa Intel Stratix 10 le Intel Arria 10 Ethernet Design Ex.amples
Bakeng sa LL 10GbE MAC Intel FPGA IP core, ha ho na matšoao a macha a hlahisoang bakeng sa lisebelisoa tsa Intel Stratix 10. Ho na le matšoao a macha a boemo bo bocha a asynchronous a hlahisitsoeng ho Intel Stratix 10 L/H-Tile Transceiver Native PHY IP Core. Phapano e sebetsa ho li-cores tsohle tsa Ethernet PHY IP, tse kenyelletsang mefuta eohle ea 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP cores le 10GBASE-R PHY Intel FPGA IP core.
Phapang ea Pontšo ea Sehokelo lipakeng tsa Intel Stratix 10 L/H-Tile Transceiver Native PHY/Multi-rate Ethernet PHY le Intel Arria 10 Transceiver Native PHY/Multi-rate Ethernet PHY
Hlokomela: = Palo ea litselana.
| Intel Stratix 10 Interface Signals | Intel Arria 10 Interface Signals | Maikutlo |
| tx_analogreset_stat[ -1
:0] |
Ha e fumanehe | Likou tsena tsa maemo a reset li sa tsoa hlahisoa lisebelisoa tsa Intel Stratix 10 feela.
Hokela ho lets'oao le ts'oanang ho Transceiver PHY Reset Controller IP core, e sebelisang tatellano e nepahetseng ea ho seta sesebelisoa. |
| rx_analogreset_stat[ -1
:0] |
Ha e fumanehe | |
| tx_digitalreset_stat[ - 1:0] | Ha e fumanehe | |
| rx_digitalreset_stat[ - 1:0] | Ha e fumanehe | |
| latency_sclk | Ha e fumanehe | Oache ea litšupiso ea ho metha nako ea morao-rao. Sampling oache bakeng sa ho metha ho lieha ha datapath ea transceiver application interface block (AIB).
Boema-kepe bona bo fumaneha ha khetho ea likou tsa tekanyo ea latency ho Intel Stratix 10 L/H-Tile Transceiver Native PHY IP core kapa khetho ea IEEE 1588 Precision Time Protocol ho 1G/ 2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA. IP core e lumelletsoe. |
| reconfig_aterese [log2
+10:0] |
reconfig_aterese [log2+9:0] | Letšoao la aterese ea tlhophiso e hokahaneng le block ea reconfiguration. Aterese bese e neng e tloaetse ho bolela aterese e lokelang ho fumaneha bakeng sa ho bala le ho ngola. |
Phapang ea Pontšo ea Sehokelo lipakeng tsa Intel Stratix 10 Transceiver Reset Controller IP le Intel Arria 10 Transceiver Reset Controller IP.
Hlokomela: = Palo ea litselana.
| Intel Stratix 10 Interface Signals | Intel Arria 10 Interface Signals | Maikutlo |
| tx_analogreset_stat[ -1
:0] |
Ha e fumanehe | Sena ke lets'oao la ho seta bocha ho tsoa ho Transceiver Native PHY IP Core. Ho na le tx_analogreset_stat e le 'ngoe ka kanale.
Ha ho netefalitsoe, ho qala tatelano ea TX PMA. Ha e hlakotsoe, seta bocha tatelano bakeng sa pheletso ea TX PMA. |
| rx_analogreset_stat[ -1
:0] |
Ha e fumanehe | Sena ke lets'oao la ho seta bocha ho tsoa ho Transceiver Native PHY IP Core. Ho na le rx_analogreset_stat e le 'ngoe ka kanale.
Ha e tiisetsoa, ho qala tatelano ea RX PMA. Ha e hlakotsoe, seta bocha tatelano bakeng sa pheletso ea RX PMA. |
| tx_digitalreset_stat[ - 1:0] | Ha e fumanehe | Sena ke lets'oao la ho seta bocha ho tsoa ho Transceiver Native PHY IP Core. Ho na le tx_digitalreset_stat e le 'ngoe ka kanale. Ha ho netefalitsoe, ho qala tatelano ea TX PCS. |
| tsoela pele. | ||
| Intel Stratix 10 Interface Signals | Intel Arria 10 Interface Signals | Maikutlo |
| Ha e hlakotsoe, seta bocha tatelano bakeng sa pheletso ea TX PCS. | ||
| rx_digitalreset_stat[ - 1:0] | Ha e fumanehe | Sena ke lets'oao la ho seta bocha ho tsoa ho Transceiver Native PHY IP Core. Ho na le rx_digitalreset_stat e le 'ngoe ka kanale.
Ha ho netefalitsoe, ho qala tatelano ea RX PCS. Ha e hlakotsoe, seta botjha tatelano bakeng sa pheletso tsa RX PCS. |
Setšoantšo se latelang se bonts'a khokahanyo ea matšoao a boemo ba ho seta bocha bakeng sa moralo oa tsamaiso ea Intel Stratix 10 Ethernet 10G. Sena se sebetsa haeba u sebelisa Intel Stratix 10 L-tile/H-tile Native PHY IP core kapa 1G/2.5G/5G/10G Multi-rate PHY Intel FPGA IP core.
Seta Setaele sa Khokahano ea Lipontšo tsa Boemo bakeng sa Intel Stratix 10 PHY IP Core le ho Seta Botjha Molaoli oa IP Core
Ho na le liphetoho tse ling ho matšoao a sebopeho sa ATX PLL le fPLL bakeng sa lisebelisoa tsa Intel Stratix 10 ha li bapisoa le lisebelisoa tsa Intel Arria 10. Haeba u falla meralo ea Ethernet ho tloha sesebelisoa sa Intel Arria 10 ho ea sesebelisoa sa Intel Stratix 10, tlosa matšoao a reset ea mcgb_rst le pll_powerdown hobane ha a fumanehe ho Intel Stratix 10.
Setšoantšo se latelang se bontša phapang pakeng tsa Intel Stratix 10 L-Tile/H-Tile ATX PLL le Intel Arria 10 ATX PLL.
Papiso lipakeng tsa Lipontšo tsa Interface bakeng sa Intel Stratix 10 L-Tile/H-Tile Transceiver ATX PLL le Intel Arria 10 Transceiver ATX PLL
Phetoho e 'ngoe ho Intel Stratix 10 L-Tile/H-Tile Transceiver PHY ke 1 biti e eketsehileng e kentsoeng beseng ea reconfig_address, ha e bapisoa le mofuta oa Intel Arria 10 Transceiver PHY. Phetoho e ts'oanang e ea hlokahala bakeng sa Multi-rate PHY kaha e etsoa ka ho sebelisa PHY ea Native joalo ka motheo.
Setšoantšo se latelang se bontša mokhoa oa ho hokahanya reconfig_address.
Thibela Setšoantšo mabapi le Khokahano ea Aterese ea Reconfiguration bakeng sa Moralo oa Intel Stratix 10 Ethernet Subsystem
Exampe bonts'itsoeng e ipapisitse le sebopeho sa Ethernet sa khaleample mohlala. Bakeng sa li-block tse hlahisoang ke Platform Designer, u ka fumana li-module ho tsoa ho moralo oa example files.
Lintlha Tse Amanang
- Intel Stratix 10 Low Latency Ethernet 10G MAC Design Example Bukana ea Mosebelisi
- Intel Stratix 10 L- le H-Tile Transceiver PHY Bukana ea Mosebelisi
- Intel Stratix 10 Clock le PLL User Guide
Phallo ea Phallo
Ke software ea Intel Quartus Prime Pro Edition feela e fanang ka meralo ea Intel Stratix 10. Haeba u sebelisa moralo oa Intel Arria 10 Ethernet ho tsoa ho Intel Quartus Prime Standard Edition, o hloka ho fallela ho mofuta oa Intel Quartus Prime Pro Edition bakeng sa moralo ofe kapa ofe oa Intel Stratix 10.
Lintlha Tse Amanang
Intel Quartus Prime Pro Handbook Handbook Volume 1: Moralo le Kopano
- E fana ka tlhaiso-leseling e batsi mabapi le ho ntlafatsa li-cores tsa IP le lits'ebetso tsa Qsys Pro ho software ea Quartus Prime Pro Edition.
Nalane ea Phetoho ea Litokomane bakeng sa AN 808
Litaelo tsa ho falla ho tloha Intel Arria 10 ho ea Intel Stratix 10 bakeng sa 10G Ethernet Subsystem.
| Tokomane Version | Liphetoho |
| 2019.11.20 | • E rehiloe bocha joalo ka Intel.
• Setšoantšo se Nchafalitsoeng: Sekema sa ho koala le ho seta bocha bakeng sa LL 10GbE MAC le 1G/2.5G/5G/10G Multi-rate Ethernet PHY Design Ex.ample (1G/2.5G Mode le IEEE 1588v2 Feature) bakeng sa Intel Stratix 10 Devices. • E entse lintlafatso tsa bohlophisi ho pholletsa le tokomane. |
| Letsatsi | Phetolelo | Liphetoho |
| Phuptjane 2017 | 2017.06.19 | Tokollo ea pele. |
AN 808: Litaelo tsa ho falla ho tloha Intel® Arria® 10 ho ea Intel® Stratix® 10 bakeng sa 10G Ethernet Subsystem.
Litokomane / Lisebelisoa
 |
Litaelo tsa ho falla ha intel ho tloha Arria 10 ho ea Stratix 10 bakeng sa 10G Ethernet Subsystem [pdf] Bukana ea Mosebelisi Litaelo tsa ho falla ho tloha Arria 10 ho ea Stratix 10 bakeng sa 10G Ethernet Subsystem, Tataiso ea ho falla, Tataiso ea ho falla ea Arria 10, Stratix 10 Tataiso ea ho falla, 10G Ethernet Subsystem Migration Guidelines |
