HDMI Arria 10 FPGA IP Design Example
Bukana ea MosebelisiHDMI Intel® Arria 10 FPGA IP
Moqapi Example Bukana ea Mosebelisi
E ntlafalitsoe bakeng sa Intel®Quartus®
Prime Design Suite: 22.4
Phetolelo ea IP: 19.7.1

HDMI Intel® FPGA IP Design Example Tataiso ea ho Qala ka Potlako bakeng sa Lisebelisoa tsa Intel® Arria® 10

Lisebelisoa tsa HDMI Intel® 10 li na le benche ea teko le moralo oa hardware o tšehetsang ho bokella le ho hlahloba lisebelisoa.
FPGA IP moralo example bakeng sa Intel Arria®
HDMI Intel FPGA IP e fana ka moralo o latelang oa mohlalaamphanyane:

• Moetso oa ho fetisa oa HDMI 2.1 RX-TX o nang le sehokelo se tsitsitseng sa sekhahla (FRL) se lumelletsoeng
• Moetso oa ho fetisa oa HDMI 2.0 RX-TX o nang le mokhoa oa FRL o koetsoeng
• HDCP holim'a moralo oa HDMI 2.0

Hlokomela: Karolo ea HDCP ha e kenyelelitsoe ho software ea Intel® Quartus Prime Pro Edition.
Ho fihlella sebopeho sa HDCP, ikopanye le Intel ho https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
Ha o hlahisa ex designample, mohlophisi oa parameter o iketsetsa faele ea files bohlokoa ho etsisa, ho bokella, le ho leka moralo ho hardware.
Setšoantšo sa 1. Mehato ea Ntšetso-peleLintlha Tse Amanang
HDMI Intel FPGA IP User Guide
1.1. Ho Hlahisa Moralo
Sebelisa HDMI Intel FPGA IP parameter editor ho Intel Quartus Prime software ho hlahisa moralo oa examples. Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
Ho qala ka Nios® II EDS ho Intel Quartus Prime Pro Edition software version 19.2 le Intel Quartus Prime Standard Edition software version 19.1, Intel e tlositse karolo ea Cygwin phetolelong ea Windows* ea Nios II EDS, ea e nkela sebaka ka Windows* Subsytem bakeng sa Linux (WSL). Haeba u mosebelisi oa Windows*, o hloka ho kenya WSL pele o etsa moralo oa hau oa khaleample.
Setšoantšo sa 2. Ho Hlahisa Phallo ea Moqapi

1. Theha morero o lebisitseng lelapa la sesebelisoa sa Intel Arria 10 ebe u khetha sesebelisoa se lakatsehang.
2. Ho IP Catalog, fumana le ho penya habeli Interface Protocols ➤ Audio & Video ➤ HDMI Intel FPGA IP. Ho hlaha fensetere e ncha ea IP Variant kapa New IP Variation.
3. Hlalosa lebitso la boemo bo holimo bakeng sa IP ea hau ea tloaelo. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file bitsetsoe .ip kapa .qsys.
4. Tobetsa OK. Mohlophisi oa parameter oa hlaha.
5. Ho tab ea IP, lokisa li-parameter tse lakatsehang bakeng sa TX le RX ka bobeli.
6. Bulela parameter ea Support FRL ho hlahisa sebopeho sa HDMI 2.1 example ka mokhoa oa FRL. E tima ho hlahisa sebopeho sa HDMI 2.0 example ntle le FRL.
7. Ka Moqapi Exampho tab, khetha Arria 10 HDMI RX-TX Retransmit.
8. Khetha Simulation ho hlahisa testbench, 'me u khethe Synthesis ho hlahisa moralo oa hardware example.U tlameha ho khetha bonyane e le 'ngoe ea likhetho tsena ho hlahisa sebopeho sa example files. Haeba u khetha ka bobeli, nako ea tlhahiso e telele.
9. Bakeng sa Hlahisa File Fomata, khetha Verilog kapa VHDL.
10. Bakeng sa Target Development Kit, khetha Intel Arria 10 GX FPGA Development Kit. Haeba u khetha sehlahisoa sa nts'etsopele, joale sesebelisoa se shebiloeng (se khethiloeng mohatong oa 4) se fetoha ho bapisa sesebelisoa se botong ea sepheo. Bakeng sa Intel Arria 10 GX FPGA Development Kit, sesebelisoa sa kamehla ke 10AX115S2F4I1SG.
11. Tobetsa Hlahisa Example Design.

Lintlha Tse Amanang
U ka kenya Windows* Subsystem bakeng sa Linux* (WSL) joang ho Windows* OS?
1.2. Ho Etsisa Moralo
The HDMI testbench e etsisa moralo oa serial loopback ho tloha mohlala oa TX ho ea ho mohlala oa RX. Jenereithara ea mokhoa oa ka hare oa video, audio sampjenereithara, jenereithara ea data ea sideband, le li-module tsa jenereithara tse thusang li khanna mohlala oa HDMI TX mme tlhahiso ea serial e tsoang ho mohlala oa TX e hokahana le mohlala oa RX sebakeng sa testbench.
Setšoantšo sa 3. Phallo ea Ketsiso ea Moralo

1. Eya ho foldara e lakatsehang ea ketsiso.
2. Matha sengoloa sa ketsiso bakeng sa simulator e tšehelitsoeng eo u e khethileng. Script e bokella le ho tsamaisa testbench ho simulator.
3. Sekaseka liphello.

Lethathamo la 1. Mehato ea ho Matha Ketsiso

Moetsisi	Bukana ea Mosebetsi	Litaelo
Riviera-PRO*	/simulation/aldec	Moleng oa taelo, thaepa
		vsim -c -do aldec.do
ModelSim*	/ketsiso/motataisi	Moleng oa taelo, thaepa
		vsim -c -do mentor.do
VCS*	/simulation/synopsy/vcs	Moleng oa taelo, thaepa
		mohloli vcs_sim.sh
Tlhaloso: VCS MX	/simulation/synopsy/ vcsmx	Moleng oa taelo, thaepa
		mohloli vcsmx_sim.sh
Xcelium* Parallel	/simulation/xcelium	Moleng oa taelo, thaepa
		mohloli xcelium_sim.sh

Ketsiso e atlehileng e qetella ka molaetsa o latelang:
# MATŠOAO_PER_CLOCK = 2
# VIC = 4
# FRL_RATE = 0
# BPP = 0
# AUDIO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Phatlalatso ea papali
1.3. Ho Kopanya le ho Lekola Moralo

Ho bokella le ho etsa tlhahlobo ea pontšo ho hardware example design, latela mehato ena:

1. Netefatsa hore hardware example tlhahiso ea moralo e felile.
2. Qala software ea Intel Quartus Prime 'me u bule .qpf file.
   • HDMI 2.1 moralo example ka Tšehetso ea FRL e nolofalitsoe: directory ea morero/quartus/a10_hdmi21_frl_demo.qpf
   • HDMI 2.0 moralo example ka Tšehetso ea FRL e holofetse: irectory/quartus/a10_hdmi2_demo.qpf
3. Tobetsa Ho sebetsa ➤ Qala ho Kopanya.
4. Ka mor'a ho bokella ka katleho, a .sof file e tla hlahisoa ka quartus/output_files directory.
5. Hokela boema-kepeng ba FMC B (J2):
   • HDMI 2.1 moralo example ka Tšehetso ea FRL e nolofalitsoe: Bitec HDMI 2.1 FMC Daughter Card Rev 9
   Hlokomela: U ka khetha ntlafatso ea karete ea morali oa Bitec HDMI ea hau. Tlas'a Moralo Example tab, beha ntlafatso ea karete ea morali oa HDMI ho Revision 9, Revision kapa ho se na karete ea morali. Boleng ba kamehla ke Revision 9.
   • HDMI 2.0 moralo example ka Tšehetso ea FRL e holofetseng: Bitec HDMI 2.0 FMC Morali oa Card Rev 11
6. Hokela TX (P1) ea karete ea morali ea Bitec FMC mohloling oa video o kantle.
7. Hokela RX (P2) ea karete ea morali ea Bitec FMC ho sinki ea kantle ea video kapa tlhahlobo ea video.
8. Netefatsa hore li-switches tsohle tse botong ea ntlafatso li maemong a kamehla.
9. Lokisa sesebelisoa sa Intel Arria 10 se khethiloeng ka har'a boto ea nts'etsopele u sebelisa tlhahiso ea .sof file (Lisebelisoa ➤ Moqapi ).
10. Mohlahlobi o lokela ho bonts'a video e hlahisitsoeng mohloling.

Lintlha Tse Amanang
Intel Arria 10 FPGA Development Kit User Guide
1.4. HDMI Intel FPGA IP Design Example Li-Parameters
Lethathamo la 2.
HDMI Intel FPGA IP Design Example Parameters ea Intel Arria 10 Devices Likhetho tsena li fumaneha bakeng sa lisebelisoa tsa Intel Arria 10 feela.

Paramethara	Boleng	Tlhaloso
Moqapi o Fumanehang Example
Kgetha Moralo	Arria 10 HDMI RX-TX Retransmit	Khetha mohlala oa moraloample tla hlahisoa.

Moqapi Example Files
Ketsiso	Bulehile, Tima	Bulela khetho ena ho etsa se hlokahalang files bakeng sa ketsiso testbench.
Synthesis	Bulehile, Tima	Bulela khetho ena ho etsa se hlokahalang files bakeng sa pokello ea Intel Quartus Prime le pontšo ea hardware.

HDL Format e entsoeng
Hlahisa File Sebopeho	Verilog, VHDL	Khetha mofuta oo u o ratang oa HDL bakeng sa sebopeho se hlahisitsoeng sa example filebeha. Hlokomela: Khetho ena e khetha feela sebopeho sa IP ea boemo bo holimo e hlahisitsoeng files. Tse ling kaofela files (mohlample testbenches le boemo bo holimo files bakeng sa pontšo ea hardware) li ka sebopeho sa Verilog HDL

Setsi sa Nts'etsopele se reriloeng
Khetha Boto	No Development Kit,	Khetha boto bakeng sa moralo o lebisitsoeng oa mohlalaample.
	Arria 10 GX FPGA Development Kit, Custom Development Kit	• No Development Kit: Khetho ena ha e kenyeletse likarolo tsohle tsa hardware bakeng sa ex designample. IP core e beha likabelo tsohle tsa pini ho li-virtual pin. • Arria 10 GX FPGA Development Kit: Khetho ena e ikhethela sesebelisoa se shebiloeng sa morero ho tsamaisana le sesebelisoa ho kit ena ea ntlafatso. U ka fetola shebiloeng sesebediswa ho sebelisa Fetola Sesebediswa se Lebeletsweng paramethara haeba tokiso ea boto ea hau e na le mofuta o fapaneng oa sesebelisoa. IP core e beha likabelo tsohle tsa phini ho latela lisebelisoa tsa nts'etsopele.
		•Custom Development Kit: Khetho ena e lumella moqapi exampe tla lekoa ho lisebelisoa tsa nts'etsopele ea motho oa boraro ka Intel FPGA. Ho ka 'na ha hlokahala hore u behe likabelo tsa phini u le mong.

Sesebediswa se reriloeng
Fetola Sesebediswa se Lebeletsweng	Bulehile, Tima	Bulela khetho ena 'me u khethe mofuta o ratoang oa sesebelisoa bakeng sa lisebelisoa tsa ntlafatso.

HDMI 2.1 Moralo Example (Ts'ehetso FRL = 1)

Moetso oa HDMI 2.1 example ka mokhoa oa FRL e bonts'a mohlala o le mong oa HDMI o ts'oanang le loopback e nang le liteishene tse 'ne tsa RX le liteishene tse nne tsa TX.
Letlapa la 3. HDMI 2.1 Moralo Example bakeng sa Intel Arria 10 Devices

Moqapi Example	Sekhahla sa Lintlha	Mokhoa oa Channel	Mofuta oa Loopback
Arria 10 HDMI RX-TX Retransmit	• 12 Gbps (FRL) • 10 Gbps (FRL) • 8Gbps (FRL) • 6 Gbps (FRL) • 3 Gbps (FRL) • <6 Gbps (TMDS)	Simplex	E tsamaisana le FIFO buffer

Likaroloana

• Moralo o tiisa li-buffers tsa FIFO ho etsa phallo e tobileng ea video ea HDMI lipakeng tsa sink ea HDMI 2.1 le mohloli.
• Moralo o khona ho chencha lipakeng tsa mokhoa oa FRL le TMDS nakong ea nako.
• Moralo o sebelisa boemo ba LED bakeng sa ho lokisa liphoso tsa peletage.
• Moralo o tla le maemo a HDMI RX le TX.
• Moralo o bonts'a ho kenngoa le ho sefa ha Dynamic Range and Mastering (HDR) InfoFrame ho mojule oa khokahanyo oa RX-TX.
• Moralo o buisana ka sekhahla sa FRL lipakeng tsa sink e hokahantsoeng le TX le mohloli o hokahantsoeng ho RX. Moralo o feta ka har'a EDID ho tloha sekoting sa kantle ho ea ho RX ea board ka tlhophiso ea kamehla. Motlakase oa Nios II o buisana ka motheo oa sehokelo mabapi le bokhoni ba sink e hokahantsoeng le TX. U ka boela ua fetola switch ea user_dipsw on-board ho laola ka bowena bokhoni ba TX le RX FRL.
• Moqapi o kenyelletsa likarolo tse 'maloa tsa ho lokisa liphoso.
  Mohlala oa RX o fumana mohloli oa video ho tsoa ho jenereithara ea kantle ea video, 'me data ebe e feta ka loopback FIFO pele e fetisetsoa ho mohlala oa TX. U hloka ho hokela sehlahlobi sa video sa kantle, monitor, kapa thelevishene e nang le khokahano ea HDMI ho mantlha ea TX ho netefatsa ts'ebetso.

2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
The HDMI RX-TX retransmit design example e bonts'a loopback e ts'oanang ho mode ea simplex ea mocha bakeng sa HDMI 2.1 e nang le tšehetso ea FRL.
Setšoantšo sa 4. HDMI 2.1 RX-TX Retransmit Block Diagram2.2. Ho theha RX-Feela kapa TX-Feela Designs
Bakeng sa basebelisi ba tsoetseng pele, u ka sebelisa moralo oa HDMI 2.1 ho etsa moralo oa TX- kapa RX-feela.
Setšoantšo sa 5. Likarolo tse Hlokehang bakeng sa RX-Feela kapa TX-Feela DesignHo sebelisa likarolo tsa RX- kapa TX-feela, tlosa li-blocks tse sa amaneng le moralo.
Letlapa la 4. Litlhoko tsa RX-Feela le TX-Feela tsa Moralo

Litlhoko tsa Mosebelisi	Boloka	Tlosa	Eketsa
HDMI RX feela	RX Top	• TX Top • Sehokelo sa RX-TX • Tsamaiso ea tsamaiso ea CPU • Transceiver Arbiter	–
HDMI TX feela	•TX Top • CPU Sub-System	•RX Top • Sehokelo sa RX-TX • Transceiver Arbiter	Jenereithara ea Paterone ea Video(mojule ea tloaelo kapa e hlahisitsoeng ho Video le Ts'ebetso ea Litšoantšo (VIP) Suite)

Ntle le liphetoho tsa RTL, o hloka ho hlophisa le mongolo oa main.c.
• Bakeng sa meralo ea HDMI TX-feela, fokotsa ho emela boemo ba senotlolo sa HDMI RX ka ho tlosa mela e latelang ebe u e nkela sebaka.
tx_xcvr_reconfig(tx_frl_rate);
rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET,
PIO_RX_LOCKED_WIDTH);
ha (rx_hdmi_lock == 0) {
haeba (check_hpd_isr()) {khefu; }
// rx_vid_lock = BALA_PIO(PIO_IN0_BASE, PIO_VID_LOCKED_OFFSET,
PIO_VID_LOCKED_WIDTH);
rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET,
PIO_RX_LOCKED_WIDTH);
// Reconfig Tx kamora hore rx e notletsoe
haeba (rx_hdmi_lock == 1) {
haeba (READ_PIO(PIO_IN0_BASE, PIO_LOOPBACK_MODE_OFFSET,
PIO_LOOPBACK_MODE_WIDTH) == 1) {
rx_frl_rate = READ_PIO(PIO_IN0_BASE, PIO_RX_FRL_RATE_OFFSET,
PIO_RX_FRL_RATE_WIDTH);
tx_xcvr_reconfig(rx_frl_rate);
} tse ling {
tx_xcvr_reconfig(tx_frl_rate);
}}}
• Bakeng sa meralo ea HDMI RX-feela, boloka feela mela e latelang ho main.c script:
REDRIVER_INIT();
hdmi_rx_init();
2.3. Litlhoko tsa Hardware le Software
Intel e sebelisa lisebelisoa tse latelang le software ho leka moralo oa example.
Lisebelisoa

• Intel Arria 10 GX FPGA Development Kit
• Mohloli oa HDMI 2.1 (Quantum Data 980 48G Generator)
• HDMI 2.1 Sink (Quantum Data 980 48G Analyzer)
• Bitec HDMI FMC 2.1 karete ea morali (Revision 9)
• Lithapo tsa HDMI 2.1 Sehlopha sa 3 (tse lekiloeng ka Belkin 48Gbps HDMI 2.1 Cable)

Software

• Intel Quartus Prime Pro Edition software version 20.1

2.4. Sebopeho sa Directory
Li-directory li na le tse hlahisitsoeng files bakeng sa sebopeho sa HDMI Intel FPGA IP example.
Setšoantšo sa 6. Sebopeho sa Directory bakeng sa Moqapi ExampleLetlapa la 5. RTL e hlahisitsoeng Files

Liphutheli	Files/Difoldara tse nyane
tloaelehileng	clock_control.ip
	clock_crosser.v
	dcfifo_inst.v
	Edge_detector.sv
	fifo.ip
	output_buf_i2c.ip

	test_pattern_gen.v
	tpg.v
	tpg_data.v
gxb	gxb_rx.ip
	gxb_rx_reset.ip
	gxb_tx.ip
	gxb_tx_fpll.ip
	gxb_tx_reset.ip
hdmi_rx	hdmi_rx.ip
	hdmi_rx_top.v
	Panasonic.hex
hdmi_tx	hdmi_tx.ip
	hdmi_tx_top.v
i2c_lekhoba	i2c_avl_mst_intf_gen.v
	i2c_clk_cnt.v
	i2c_condt_det.v
	i2c_databuffer.v
	i2c_rxshifter.v
	i2c_slvfsm.v
	i2c_spksuppp.v
	i2c_txout.v
	i2c_txshifter.v
	i2cslave_to_avlmm_bridge.v
pll	pll_hdmi_reconfig.ip
	pll_frl.ip
	pll_reconfig_ctrl.v
	pll_tmds.ip
	pll_vidclk.ip
	quartus.ini
rxtx_link	altera_hdmi_hdr_infoframe.v
	aux_mux.qsys
	aux_retransmit.v
	aux_src_gen.v
	ext_aux_filter.v

	rxtx_link.v
	scfifo_vid.ip
reconfig	mr_rx_iopll_tmds/
	mr_rxphy/
	mr_tx_fpll/
	altera_xcvr_functions.sv
	mr_compare.sv
	mr_rate_detect.v
	mr_rx_rate_detect_top.v
	mr_rx_rcfg_ctrl.v
	mr_rx_reconfig.v
	mr_tx_rate_detect_top.v
	mr_tx_rcfg_ctrl.v
	mr_tx_reconfig.v
	rcfg_array_streamer_iopll.sv
	rcfg_array_streamer_rxphy.sv
	rcfg_array_streamer_rxphy_xn.sv
	rcfg_array_streamer_txphy.sv
	rcfg_array_streamer_txphy_xn.sv
	rcfg_array_streamer_txpll.sv
sdc	a10_hdmi2.sdc
	jtag.sdc

Lethathamo la 6. Ketsiso e hlahisitsoeng Files
Sheba ho Ketsiso Testbench karolo bakeng sa tlhahisoleseding e eketsehileng

Liphutheli	Files
aldec	/aldec.do
	/rivierapro_setup.tcl
cadence	/cds.lib
	/hdl.var
motataisi	/mentor.etsa
	/msim_setup.tcl
li-synopsy	/vcs/filelenane.f
	/vcs/vcs_setup.sh

	/vcs/vcs_sim.sh
	/vcsmx/synopsys_sim_setup
	/vcsmx/vcsmx_setup.sh
	/vcsmx/vcsmx_sim.sh
xcelium	/cds.lib
	/hdl.var
	/xcelium_setup.sh
	/xcelium_sim.sh
tloaelehileng	/mohlala_files.tcl
	/riviera_files.tcl
	/vcs_files.tcl
	/vcsmx_files.tcl
	/xcelium_files.tcl
hdmi_rx	/hdmi_rx.ip
	/Panasonic.hex
hdmi_tx	/hdmi_tx.ip

Lethathamo la 7. Software e hlahisitsoeng Files

Liphutheli	Files
tx_control_src Hlokomela: Foldara ea tx_control e boetse e na le tse kopitsoang tsa tsena files.	lefatše lohle.h
	hdmi_rx.c
	hdmi_rx.h
	hdmi_tx.c
	hdmi_tx.h
	hdmi_tx_read_edid.c
	hdmi_tx_read_edid.h
	Intel_fpga_i2c.c
	intel_fpga_i2c.h
	ka sehloohong.c
	pio_bala_write.c
	pio_bala_ngola.h

2.5. Likarolo tsa Moqapi
Moetso oa HDMI Intel FPGA IP example e na le likarolo tse tloaelehileng tsa boemo bo holimo le HDMI TX le likarolo tse ka holimo tsa RX.
2.5.1. Likarolo tsa HDMI TX
Likarolo tse kaholimo tsa HDMI TX li kenyelletsa likarolo tsa boemo bo holimo ba TX, le IOPLL, transceiver PHY reset controller, transceiver native PHY, TX PLL, TX reconfiguration management, le li-block buffer tse hlahisoang.
Setšoantšo sa 7. HDMI TX Top ComponentsLetlapa la 8. HDMI TX Top Components

Mojule	Tlhaloso
HDMI TX Core	IP e amohela data ea video ho tloha boemong bo holimo 'me e etsa encoding ea data, audio data encoding, video encoding, scrambling, TMDS encoding kapa packetization.
IOPLL	IOPLL (iopll_frl) e hlahisa oache ea FRL bakeng sa mantlha ea TX. Oache ena ea litšupiso e amohela oache ea tlhahiso ea TX FPLL. Leqhubu la oache ea FRL = Sekhahla sa data ka litselana x 4 / (litlhaku tsa FRL ka oache x 18)
Transceiver PHY Reset Controller	Transceiver PHY reset controller e netefatsa ho qalisoa ho tšepahalang ha li-transceivers tsa TX. Kenyelletso ea ho tsosolosa ea molaoli enoa e hlahisoa ho tloha boemong bo phahameng, 'me e hlahisa letšoao le lumellanang la analog le digital reset ho Transceiver Native PHY thibela ho ea ka tatellano ea ho tsosolosa ka hare ho thibela. Letšoao la tlhahiso ea tx_ready ho tloha thibela ena e boetse e sebetsa e le pontšo ea ho tsosolosa HDMI Intel FPGA IP ho bontša hore transceiver e ntse e sebetsa, 'me e itokiselitse ho fumana data ho tloha bohareng.
Transceiver Native PHY	Hard transceiver block e amohelang data e ts'oanang ho tsoa ho mantlha ea HDMI TX mme e hlophisa data ho tsoa ho e fetisetsa. Hlokomela: Ho kopana le tlhokeho ea HDMI TX inter-channel skew, beha khetho ea mokhoa oa TX bonding ho Intel Arria 10 Transceiver Native PHY parameter editor ho PMA le PCS tlamahano. U boetse u hloka ho eketsa tlhoko ea skew (set_max_skew) ho lets'oao la reset ea dijithale ho tsoa ho transceiver reset controller (tx_digitalreset) joalo ka ha ho khothalelitsoe ho Intel Arria 10 Transceiver PHY User Guide.
TX PLL	Transmitter PLL block e fana ka oache e potlakileng ea serial ho Transceiver Native PHY block. Bakeng sa sebopeho sena sa HDMI Intel FPGA IP example, fPLL e sebelisoa joalo ka TX PLL. TX PLL e na le lioache tse peli tsa litšupiso. • Tshupanako ya tshupanako 0 e hoketswe ho oscillator e ka hlophisehang (ka maqhubu a watjhe ya TMDS) bakeng sa mokgwa wa TMDS. Moqaping ona example, RX TMDS oache e sebelisoa ho hokela oacheng ea referense 0 bakeng sa mokhoa oa TMDS. Intel eu khothalletsa hore u sebelise oscillator e hlophisitsoeng e nang le maqhubu a oache ea TMDS bakeng sa oache ea tšupiso 0. • Oache ea tšupiso ea 1 e hoketsoe ho oache e tsitsitseng ea 100 MHz bakeng sa mokhoa oa FRL.
TX Reconfiguration Management	•Ka mokhoa oa TMDS, thibelo ea tsamaiso ea TX reconfiguration e tsosolosa TX PLL bakeng sa maqhubu a fapaneng a tlhahiso ea oache ho latela maqhubu a oache ea TMDS ea video e itseng. •Ka mokhoa oa FRL, TX reconfiguration management block e tsosolosa TX PLL ho fana ka oache e potlakileng ea serial bakeng sa 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps le 12 Gbps ho latela sebaka sa FRL_Rate bukeng ea 0x31 SCDC. •Setsi sa tsamaiso ea TX reconfiguration se fetola oache ea tšupiso ea TX PLL pakeng tsa oache ea boitsebiso 0 bakeng sa mokhoa oa TMDS le oache ea 1 bakeng sa mokhoa oa FRL.
Khumo buffer	Buffer ena e sebetsa e le sebopeho sa ho sebelisana le I2C interface ea HDMI DDC le likarolo tsa ho khanna.

Lethathamo la 9.Sekhahla sa Boitsebiso ba Transceiver le Oversampling Factor Clock E 'ngoe le e 'ngoe Frequency Range

Mokhoa	Sekhahla sa Lintlha	Ho fetaampsebaka sa 1 (2x oversample)	Ho fetaampsebaka sa 2 (4x oversample)	Ho fetaample Ntlha	Ho fetaampLed Data Rate (Mbps)
TMDS	250–1000	On	On	8	2000–8000
TMDS	1000–6000	On	E tima	2	2000–12000
FRL	3000	E tima	E tima	1	3000
FRL	6000	E tima	E tima	1	6000

FRL	8000	E tima	E tima	1	8000
FRL	10000	E tima	E tima	1	10000
FRL	12000	E tima	E tima	1	12000

Setšoantšo sa 8. TX Reconfiguration Sequence Flow2.5.2. Likarolo tsa HDMI RX
Likarolo tse kaholimo tsa HDMI RX li kenyelletsa likarolo tsa boemo bo holimo tsa RX, lekhoba la I²C le EDID RAM, IOPLL, transceiver PHY reset controller, RX native PHY, le lithibelo tsa taolo ea phetisetso ea RX.
Setšoantšo sa 9. HDMI RX Top ComponentsLetlapa la 10. HDMI RX Top Components

Mojule	Tlhaloso
HDMI RX Core	IP e amohela lintlha tsa serial ho tsoa ho Transceiver Native PHY 'me e etsa ho hokahanya ha data, deskew ea kanal, decoding TMDS, decoding data decoding, video decoding, audio data decoding, and descrambling.
I2C Lekhoba	I2C ke sebopeho se sebelisoang bakeng sa Sink Display Data Channel (DDC) le Status le Data Channel (SCDC). Mohloli oa HDMI o sebelisa DDC ho fumana bokhoni le litšobotsi tsa sink ka ho bala sebopeho sa data se Enhanced Extended Display Identification Data (E-EDID). Liaterese tsa 8-bit I2C tsa makhoba tsa E-EDID ke 0xA0 le 0xA1. LSB e bontša mofuta oa phihlello: 1 bakeng sa ho bala le 0 bakeng sa ho ngola. Ha ketsahalo ea HPD e etsahala, lekhoba la I2C le arabela ho data ea E-EDID ka ho bala ho tloha ho-chip Molaoli oa makhoba feela oa I2C o boetse o tšehetsa SCDC bakeng sa HDMI 2.0 le 2.1 Aterese ea lekhoba la 9-bit I2C bakeng sa SCDC ke 0xA8 le 0xA9. Ha ketsahalo ea HPD e etsahala, lekhoba la I2C le etsa transaction ea ho ngola kapa ho bala ho tloha kapa ho tloha SCDC segokanyimmediamentsi sa sebolokigolo HDMI RX. Ts'ebetso ea lithupelo tsa khokahanyo bakeng sa Fixed Rate Link (FRL) e boetse e etsahala ka I2C Nakong ea ketsahalo ea HPD kapa ha mohloli o ngola tekanyo e fapaneng ea FRL ho ngoliso ea FRL Rate (SCDC e ngolisa 0x31 bit [3: 0]), mokhoa oa koetliso oa li-link o qala. Hlokomela: Taolo ena ea makhoba feela ea I2C bakeng sa SCDC ha e hlokehe haeba HDMI 2.0 kapa HDMI 2.1 e sa rereloa.

EDID RAM

Moralo o boloka tlhahisoleseling ea EDID o sebelisa RAM 1-Port IP. Mokhoa o tloaelehileng oa terata e 'meli (oache le data) serial bus protocol (I2C lekhoba-feela molaoli) o fetisetsa sebopeho sa data sa CEA-861-D Compliant E-EDID. EDID RAM ena e boloka lintlha tsa E-EDID. •Ha o le mokgweng wa TMDS, moralo o tshehetsa ho feta ha EDID ho tloha TX ho ya ho RX. Nakong ea ho feta ha EDID, ha TX e hokahane le sekoting sa kantle, processor ea Nios II e bala EDID ho tsoa sekoting sa kantle ebe e ngolla EDID RAM. • Ha e le maemong a FRL, processor ea Nios II e ngola EDID e lokiselitsoeng esale pele bakeng sa sekhahla se seng le se seng sa lihokelo ho ipapisitse le paramethara ea HDMI_RX_MAX_FRL_RATE ho mongolo oa global.h. Sebelisa tse latelang HDMI_RX_MAX_FRL_RATE bakeng sa reiti e tšehetsoeng ea FRL: • 1: 3G 3 Litsela • 2: 6G 3 Litsela • 3: 6G 4 Litsela • 4: 8G 4 Litsela •5: 10G 4 Lane (ea kamehla) • 6: 12G 4 Litsela

IOPLL

HDMI RX e sebelisa li-IOPLL tse peli. • IOPLL ea pele (pll_tmds) e hlahisa oache ea litšupiso ea RX CDR. IOPLL ena e sebelisoa feela ka mokhoa oa TMDS. Oache ea litšupiso ea IOPLL ena e amohela oache ea TMDS. Mokhoa oa TMDS o sebelisa IOPLL ena hobane CDR ha e khone ho fumana lioache tsa litšupiso tse ka tlase ho 50 MHz mme maqhubu a oache ea TMDS a tloha ho 25 MHz ho isa ho 340 MHz. IOPLL ena e fana ka maqhubu a oache ao e leng linako tse 5 tsa oache ea ts'ebeliso ea nako e pakeng tsa 25 MHz ho isa ho 50 MHz mme e fana ka maqhubu a oache a tšoanang le oache ea ts'ebeliso ea nako e pakeng tsa 50 MHz ho 340 MHz. •IOPLL ea bobeli (iopll_frl) e hlahisa oache ea FRL bakeng sa mokokotlo oa RX. Oache ena ea litšupiso e amohela oache e khutlisitsoeng ea CDR. Leqhubu la oache ea FRL = Sekhahla sa data ka litselana x 4 / (litlhaku tsa FRL ka oache x 18)

Transceiver PHY Reset Controller	Transceiver PHY reset controller e netefatsa ts'ebetso e tšepahalang ea li-transceivers tsa RX. Tlhaloso ea ho tsosolosa ea molaoli enoa e bakoa ke ho tsosolosoa ha RX, 'me e hlahisa letšoao le lumellanang la analog le digital reset ho Transceiver Native PHY thibela ho ea ka tatellano ea ho tsosolosa ka hare ho thibela.
RX Native PHY	Hard transceiver block e amohelang data ea serial ho tsoa mohloling oa video o kantle. E senya data ea serial ho data e tšoanang pele e fetisetsa data ho HDMI RX core. Sebaka sena se sebetsa ho Enhanced PCS bakeng sa mokhoa oa FRL. RX CDR e na le lioache tse peli tsa litšupiso. • Oache ea litšupiso 0 e hoketsoe ho oache ea tlhahiso ea IOPLL TMDS (pll_tmds), e nkiloeng ho tsoa ho TMDS. • Oache ea tšupiso ea 1 e hoketsoe ho oache e tsitsitseng ea 100 MHz. Ka mokhoa oa TMDS, RX CDR e lokisoa bocha ho khetha oache ea tšupiso 0, 'me ka mokhoa oa FRL, RX CDR e lokisoa bocha ho khetha oache ea tšupiso 1.
Tsamaiso ea Reconfiguration ea RX	Ka mokhoa oa TMDS, thibelo ea tsamaiso ea RX reconfiguration e sebelisa sekhahla sa ho lemoha sekhahla le HDMI PLL ho khanna transceiver ea RX ho sebetsa ka litekanyetso leha e le life tsa khokahanyo ho tloha ho 250 Mbps ho ea ho 6,000 Mbps. Ka mokhoa oa FRL, thibelo ea tsamaiso ea RX reconfiguration e tsosolosa transceiver ea RX hore e sebetse ho 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, kapa 12 Gbps ho itšetlehile ka tekanyo ea FRL sebakeng sa ngoliso sa SCDC_FRL_RATE (0x31 [3: 0]). Thibelo ea taolo ea ntlafatso ea RX e fetoha lipakeng tsa Standard PCS/RX bakeng sa mokhoa oa TMDS le PCS e ntlafalitsoeng bakeng sa mokhoa oa FRL.Sheba ho Setšoantšo sa 10 leqepheng la 22.

Setšoantšo sa 10. Phallo ea Tatelano ea Reconfiguration ea RX
Palo e bonts'a phallo ea tatellano ea li-reconfiguration tse ngata tsa molaoli ha a amohela phallo ea data e kentsoeng le maqhubu a oache ea litšupiso, kapa ha transceiver e notletsoe.2.5.3. Li-blocks tse tloaelehileng tsa boemo bo holimo
Li-blocks tse tloaelehileng tse maemong a holimo li kenyelletsa arbiter ea transceiver, likarolo tsa khokahano ea RX-TX, le sistimi e nyane ea CPU.
Lethathamo la 11. Li-blocks tse tloaelehileng tsa boemo bo holimo

Mojule

Tlhaloso

Transceiver Arbiter

Sebaka sena sa generic se thibelang li-transceivers ho tsosolosa ka nako e le 'ngoe ha li-transceivers tsa RX kapa TX ka har'a mocha o tšoanang oa' mele o hloka ho tsosolosoa. Ho tsosolosoa ha nako e le 'ngoe ho ama lits'ebetso moo li-transceivers tsa RX le TX ka har'a mocha o le mong li abeloang ho kenya ts'ebetsong e ikemetseng ea IP. Transceiver arbiter ena ke katoloso ea qeto e khothaletsoang bakeng sa ho kopanya simplex TX le simplex RX mocheng o tšoanang oa 'mele. Setsebi sena sa transceiver se boetse se thusa ho kopanya le ho rarolla likopo tsa RX le TX tse lebisitsoeng ho li-transceivers tse lebisitsoeng ho simplex RX le TX ka har'a mocha kaha boema-kepe ba li-transceivers bo ka fihlelleha ka tatellano feela. Khokahano pakeng tsa transceiver arbiter le TX/RX Native PHY/PHY Reset Controller e thibela sebopeho sena sa khale.ample e bonts'a mokhoa oa generic o sebetsang bakeng sa motsoako ofe kapa ofe oa IP o sebelisang transceiver arbiter. Transceiver arbiter ha e hlokehe ha feela RX kapa TX transceiver e sebelisoa kanaleng. Transceiver arbiter e tsebahatsa mokopi oa tokiso bocha ka li-interface tsa eona tsa mohopolo oa Avalon mme o netefatsa hore tx_reconfig_cal_busy kapa rx_reconfig_cal_busy e tsamaellanang e kentsoe ka nepo. Bakeng sa lits'ebetso tsa HDMI, ke RX feela e qalang ho hlophisa bocha. Ka ho fana ka kopo ea ntlafatso ea 'mapa oa mohopolo oa Avalon ka mohanyetsi, mohanyetsi o tsebahatsa hore kopo ea ntlafatso e tsoa ho RX, e ntan'o thibela tx_reconfig_cal_busy ho tiisa le ho lumella rx_reconfig_cal_busy ho bolela. Keiti e thibela transceiver ea TX ho fallisetsoa mokhoeng oa ho lekanya e sa rera. Hlokomela: Hobane HDMI e hloka feela ho hlophisoa bocha ha RX, matšoao a tx_reconfig_mgmt_* a tlameletsoe. Hape, sebopeho sa 'mapa oa Avalon ha se hlokehe lipakeng tsa arbiter le block ea TX Native PHY. Li-blocks li abeloa sebopeho sa sebopeho sa example ho bonts'a khokahano ea generic transceiver arbiter ho TX/RX Native PHY/PHY Reset Controller

Sehokelo sa RX-TX

• Poelo ya data ya video le matshwao a kamahanyo ho tswa ho HDMI RX core loop ka DCFIFO ho phatlalla le dioache tsa video tsa RX le TX. • Boema-kepe bo thusang ba HDMI TX core bo laola lintlha tse thusang tse phallang ka DCFIFO ka khatello ea morao. The backpressure e tiisa hore ha ho na pakete e thusang e sa fellang boema-kepeng ba data bo thusang. • Sebaka sena se boetse se etsa sefa sa kantle: - E sefa data ea molumo le pakete ea nchafatso ea oache ea molumo ho tsoa mohloling oa data o thusang pele o fetisetsa koung ea data e thusang ea HDMI TX. - Filters the High Dynamic Range (HDR) InfoFrame ho tsoa ho HDMI RX data e thusang ebe e kenya ex.ample HDR InfoFrame ho data e thusang ea HDMI TX ka Avalon streaming multiplexer.

Sistimi e nyane ea CPU

Setsi sa tšebetso sa CPU se sebetsa joalo ka balaoli ba SCDC le DDC, le taolo ea ntlafatso ea mohloli. • Mohloli oa taolo ea SCDC o na le I2C master controller. Molaoli ea hloahloa oa I2C o fetisetsa sebopeho sa data sa SCDC ho tloha mohloling oa FPGA ho ea sekoting sa kantle bakeng sa ts'ebetso ea HDMI 2.0. Bakeng sa mohlalaample, haeba data e tsoang e le 6,000 Mbps, processor ea Nios II e laela molaoli ea ka sehloohong oa I2C ho nchafatsa likotoana tsa TMDS_BIT_CLOCK_RATIO le SCRAMBLER_ENABLE tsa rejisetere ea tlhophiso ea sink TMDS ho 1. • Monghali ea tšoanang oa I2C o boetse o fetisetsa sebopeho sa data sa DDC (E-EDID) pakeng tsa mohloli oa HDMI le sink e ka ntle. • Nios II CPU e sebetsa e le molaoli oa ho tsosolosa mohloli oa HDMI. CPU e ipapisitse le tlhahlobo ea sekhahla sa nako le nako ho tsoa mojuleng oa Tsamaiso ea Reconfiguration ea RX ho fumana hore na TX e hloka ho lokisoa bocha. Mofetoleli oa makhoba a 'mapa oa mohopolo oa Avalon o fana ka khokahano lipakeng tsa processor ea Nios II Avalon-mapped master interface le Avalon memory-mapped lekhoba interfaces tsa kantle tse kentsoeng HDMI mohloli oa IOPLL le TX Native PHY. • Etsa lithupelo tsa lihokelo ka I2C master interface le sink ea kantle

2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
Moetso oa HDMI Intel FPGA IP example kenyeletsa pontšo ea ho kenngoa ha HDR InfoFrame ho RX-TX loopback system.
HDMI Specification version 2.0b e lumella Dynamic Range le Mastering InfoFrame hore e fetisetsoe ka HDMI e thusang. Pontšong, thibela ea Auxiliary Packet Generator e tšehetsa ho kenngoa ha HDR. U hloka feela ho fomata sephutheloana se reriloeng sa HDR InfoFrame joalo ka ha ho boletsoe tafoleng ea lenane la matšoao a module le ho kenya HDR InfoFrame ho etsahala hang ha foreimi e 'ngoe le e 'ngoe ea video.
Ho sena mohlalaample tlhophiso, maemong ao molapo o thusang o kenang o se o ntse o kenyelletsa HDR InfoFrame, litaba tsa HDR tse phatlalalitsoeng lia sefuoa. Sefa se qoba likhohlano tsa HDR InfoFrames hore li fetisoe mme e netefatsa hore ke litekanyetso tse boletsoeng feela ho HDR S.ample Data module li sebelisoa.
Setšoantšo sa 11. RX-TX Link le Dynamic Range le Mastering InfoFrame Insertion
Setšoantšo se bonts'a setšoantšo sa block sa sehokelo sa RX-TX se kenyelletsang Dynamic Range le Mastering InfoFrame ho kenyelletsoa ho molapo o thusang oa mantlha oa HDMI TX.Letlapa la 12. Thibelo ea ho Kenyeletsoa ha Boitsebiso (aux_retransmit) Lipontšo

Letshwao	Tataiso	Bophara	Tlhaloso
Oache 'me Reset
clk	Kenyeletso	1	Kenyelletso ea oache. Oache ena e lokela ho hokela oacheng ea video.
tsosolosa	Kenyeletso	1	Seta bocha.

Lipontšo tsa Pakete tse thusang
tx_aux_data	Sephetho	72	Phakete ea TX e thusang ho tsoa ho multiplexer.
tx_aux_valid	Sephetho	1
tx_aux_ready	Sephetho	1
tx_aux_sop	Sephetho	1
tx_aux_eop	Sephetho	1
rx_aux_data	Kenyeletso	72	Lintlha tse thusang tsa RX li fetiselitsoe mojuleng oa filthara ea pakete pele o kenya multiplexer.
rx_aux_valid	Kenyeletso	1
rx_aux_sop	Kenyeletso	1
rx_aux_eop	Kenyeletso	1

Pontšo ea taolo
hdmi_tx_vsync	Kenyeletso	1	HDMI TX Video Vsync. Lets'oao lena le lokela ho amahanngoa le sebaka sa lebelo la sehokelo sa oache.Moko oa mantlha o kenya HDR InfoFrame ho molapo o thusang pheletsong e holimo ea lets'oao lena.

Lethathamo la 13. Lipontšo tsa HDR Data Module (altera_hdmi_hdr_infoframe)

Letshwao	Tataiso	Bophara	Tlhaloso
hb0	Sephetho	8	Header byte 0 ea Dynamic Range le Mastering InfoFrame: khoutu ea mofuta oa InfoFrame.
hb1	Sephetho	8	Header byte 1 ea Dynamic Range le Mastering InfoFrame: Nomoro ea mofuta oa InfoFrame.
hb2	Sephetho	8	Header byte 2 ea Dynamic Range le Mastering InfoFrame: Length of InfoFrame.
pb	Kenyeletso	224	Data byte ea Dynamic Range le Mastering InfoFrame.

Letlapa la 14. Dynamic Range le Mastering InfoFrame Data Byte Bundle Bit-Fields

Sebaka se senyenyane	Tlhaloso	Mofuta oa 1 oa Static Metadata
7:0	Data Byte 1: {5'h0, EOTF[2:0]}
15:8	Data Byte 2: {5'h0, Static_Metadata_Descriptor_ID[2:0]}
23:16	Data Byte 3: Static_Metadata_Descriptor	display_primaries_x[0], LSB
31:24	Data Byte 4: Static_Metadata_Descriptor	display_primaries_x[0], MSB
39:32	Data Byte 5: Static_Metadata_Descriptor	display_primaries_y[0], LSB
47:40	Data Byte 6: Static_Metadata_Descriptor	display_primaries_y[0], MSB
55:48	Data Byte 7: Static_Metadata_Descriptor	display_primaries_x[1], LSB
63:56	Data Byte 8: Static_Metadata_Descriptor	display_primaries_x[1], MSB
71:64	Data Byte 9: Static_Metadata_Descriptor	display_primaries_y[1], LSB
79:72	Data Byte 10: Static_Metadata_Descriptor	display_primaries_y[1], MSB
87:80	Data Byte 11: Static_Metadata_Descriptor	display_primaries_x[2], LSB
95:88	Data Byte 12: Static_Metadata_Descriptor	display_primaries_x[2], MSB
103:96	Data Byte 13: Static_Metadata_Descriptor	display_primaries_y[2], LSB
111:104	Data Byte 14: Static_Metadata_Descriptor	display_primaries_y[2], MSB
119:112	Data Byte 15: Static_Metadata_Descriptor	white_point_x, LSB
127:120	Data Byte 16: Static_Metadata_Descriptor	white_point_x, MSB
135:128	Data Byte 17: Static_Metadata_Descriptor	white_point_y, LSB
143:136	Data Byte 18: Static_Metadata_Descriptor	white_point_y, MSB
151:144	Data Byte 19: Static_Metadata_Descriptor	max_display_mastering_luminance, LSB

159:152	Data Byte 20: Static_Metadata_Descriptor	max_display_mastering_luminance, MSB
167:160	Data Byte 21: Static_Metadata_Descriptor	min_display_mastering_luminance, LSB
175:168	Data Byte 22: Static_Metadata_Descriptor	min_display_mastering_luminance, MSB
183:176	Data Byte 23: Static_Metadata_Descriptor	Boemo bo phahameng ba Leseli, LSB
191:184	Data Byte 24: Static_Metadata_Descriptor	Boemo bo phahameng ba Leseli la Boitsebiso, MSB
199:192	Data Byte 25: Static_Metadata_Descriptor	Boemo bo phahameng ba Frame-average Light Level, LSB
207:200	Data Byte 26: Static_Metadata_Descriptor	Maximum Frame-average Light Level, MSB
215:208	Reserved
223:216	Reserved

E thibela ho Kenya le ho Filtering ea HDR
Ho thibela ho kenya HDR le filthara ho u thusa ho netefatsa phetiso ea litaba tsa HDR tse seng li ntse li fumaneha mohloling o thusang ntle le phetoho ho RX-TX Retransmit design ex.ample.
Ho tima ho kenya le ho sefa HDR InfoFrame:

1. Beha block_ext_hdr_infoframe ho 1'b0 ho rxtx_link.v file ho thibela ho sefa ha HDR InfoFrame ho tsoa ho Auxiliary stream.
2. Beha multiplexer_in0_valid ea avalon_st_multiplexer ho altera_hdmi_aux_hdr.v file ho 1'b0 ho thibela Auxiliary Packet Generator ho theha le ho kenya HDR InfoFrame e eketsehileng ho TX Auxiliary stream.

2.7. Moqapi oa Phallo ea Software
Phallong ea mantlha ea software ea moralo, processor ea Nios II e hlophisa tlhophiso ea boits'oaro ba TI mme e qala litsela tsa TX le RX holim'a matla.
Setšoantšo sa 12. Phallo ea Software ho main.c Script
Software e etsa loop ea nakoana ho lekola sink le liphetoho tsa mohloli, le ho arabela liphetohong. Software e ka 'na ea tsosa TX reconfiguration, koetliso ea khokahano ea TX' me ea qala ho fetisa video.
Setšoantšo sa 13. TX Path Initialization Flowchart Qala TX TselaSetšoantšo sa 14. RX Path Initialization FlowchartSetšoantšo sa 15. TX Reconfiguration and Link Training FlowchartSetšoantšo sa 16. Khokahano ea Koetliso ea LTS: Ts'ebetso ea 3 ho Specific FRL Rate FlowchartSetšoantšo sa 17. HDMI TX Phallo ea Phallo ea Video2.8. Ho tsamaisa Moralo ka Litefiso tse fapaneng tsa FRL
O ka tsamaisa moralo oa hau ka litefiso tse fapaneng tsa FRL, ntle le sekhahla sa kamehla sa sinki sa FRL.
Ho tsamaisa moralo ka litefiso tse fapaneng tsa FRL:

1. Fetolela on-board user_dipsw0 switjha hore e be ON.
2. Bula khetla ea taelo ea Nios II, ebe u thaepa nios2-terminal
3. Konopo litaelong tse latelang ebe o tobetsa Enter ho phethahatsa.

Taelo	Tlhaloso
h	Hlahisa lenane la thuso.
r0	Nchafatsa bokhoni ba RX bo phahameng ba FRL ho sekhahla sa FRL 0 (TMDS feela).
r1	Nchafatsa bokhoni ba RX bo phahameng ba FRL ho sekhahla sa FRL 1 (3 Gbps).
r2	Nchafatsa bokhoni ba RX bo phahameng ba FRL ho sekhahla sa FRL 2 (6 Gbps, 3 lane).
r3	Nchafatsa bokhoni ba RX bo phahameng ba FRL ho sekhahla sa FRL 3 (6 Gbps, 4 lane).
r4	Nchafatsa bokhoni ba RX bo phahameng ba FRL ho sekhahla sa FRL 4 (8 Gbps).
r5	Nchafatsa bokhoni ba RX bo phahameng ba FRL ho sekhahla sa FRL 5 (10 Gbps).
r6	Nchafatsa bokhoni ba RX bo phahameng ba FRL ho sekhahla sa FRL 6 (12 Gbps).
t1	TX e hlophisa sekhahla sa khokahano ho sekhahla sa FRL 1 (3 Gbps).
t2	TX e hlophisa sekhahla sa khokahano ho sekhahla sa FRL 2 (6 Gbps, litselana tse 3).
t3	TX e hlophisa sekhahla sa khokahano ho sekhahla sa FRL 3 (6 Gbps, litselana tse 4).
t4	TX e hlophisa sekhahla sa khokahano ho sekhahla sa FRL 4 (8 Gbps).
t5	TX e hlophisa sekhahla sa khokahano ho sekhahla sa FRL 5 (10 Gbps).
t6	TX e hlophisa sekhahla sa khokahano ho sekhahla sa FRL 6 (12 Gbps).

2.9. Sekema sa ho Tlisa
Sekema sa oache se bonts'a libaka tsa oache ho HDMI Intel FPGA IP design example.
Setšoantšo sa 18. HDMI 2.1 Design Example Clock SchemeLetlapa la 15. Lipontšo tsa Scheme ea ho Tsupa

Tshupanako	Lebitso la Letshwao ka Moralo	Tlhaloso
Oache ea Tsamaiso	mgmt_clk	Oache ea mahala ea 100 MHz bakeng sa likarolo tsena: • Lihokelo tsa Avalon-MM bakeng sa ho hlophisoa bocha - Tlhokahalo ea maqhubu a maqhubu a pakeng tsa 100-125 MHz. • PHY seta botjha taolo bakeng sa tatelano ya ho seta botjha ha transceiver - Lebelo la maqhubu a hlokahalang ke pakeng tsa 1-500 MHz. • IOPLL Reconfiguration - Nako e phahameng ea nako ea oache ke 100 MHz. • RX Reconfiguration Management • TX Reconfiguration Management • CPU • I2C Master
Clock ea I2C	i2c_clk	Kenyelletso ea oache ea 100 MHz e ts'oarang lekhoba la I2C, li-buffers, li-register tsa SCDC, le ts'ebetso ea khokahanyo ea koetliso mokokotlong oa HDMI RX, le EDID RAM.
TX PLL Reference Clock 0	tx_tmds_clk	Tshupanako ya 0 ho TX PLL. Leqhubu la oache le ts'oana le lebelo le lebelletsoeng la oache ea TMDS ho tsoa ho kanaleng ea oache ea HDMI TX TMDS. Oache ena ea litšupiso e sebelisoa ka mokhoa oa TMDS. Bakeng sa sebopeho sena sa HDMI example, oache ena e hokahane le oache ea RX TMDS ka sepheo sa pontšo. Ts'ebelisong ea hau, o hloka ho fana ka oache e inehetseng e nang le maqhubu a oache ea TMDS ho tsoa ho oscillator e ka khonehang bakeng sa ts'ebetso e ntle ea jitter.

		Hlokomela: Se ke oa sebelisa transceiver RX pin joalo ka oache ea litšupiso ea TX PLL. Moralo oa hau o tla hloleha ho lekana haeba o beha HDMI TX refclk ho phini ea RX.
TX PLL Reference Clock 1	txfpll_refclk1/ rxphy_cdr_refclk1	Oache ea litšupiso ho TX PLL le RX CDR, hammoho le IOPLL bakeng sa vid_clk. Lebelo la oache ke 100 MHz.
TX PLL Serial Clock	tx_bonding_clocks	Oache e potlakileng e hlahisoang ke TX PLL. Maqhubu a oache a behiloe ho ipapisitsoe le sekhahla sa data.
TX Transceiver Clock Out	tx_clk	Clock out e hlaphohetsoe ho transceiver, 'me maqhubu a fapana ho latela sekhahla sa data le matšoao ka oache. TX transceiver clock out frequency = Sekhahla sa data ea Transceiver/ Bophara ba Transceiver Bakeng sa sebopeho sena sa HDMI example, oache ea transceiver ea TX e tsoang kanaleng 0 e ts'oara sesupa-nako sa TX transceiver core input (tx_coreclkin), sesupanako sa sehokelo sa IOPLL (pll_hdmi), le oache ea litšupiso ea video le FRL IOPLL (pll_vid_frl).
Oache ea Video	tx_vid_clk/rx_vid_clk	Oache ea video ho TX le RX core. Oache e matha ka lebelo le tsitsitseng la 225 MHz.
Oache ea TX/RX FRL	tx_frl_clk/rx_frl_clk	Oache ea FRL ho ea ho TX le RX core.
Oache ea RX TMDS	rx_tmds_clk	Kanale ea oache ea TMDS ho tsoa ho sehokelo sa HDMI RX mme e hokela ho IOPLL ho hlahisa oache ea litšupiso bakeng sa oache ea litšupiso ea CDR 0. Konopo e sebelisa oache ena ha e le maemong a TMDS.
RX CDR Reference Clock 0	rxphy_cdr_refclk0	Tshupanako ya 0 ho ya ho RX CDR. Oache ena e nkiloe ho oache ea RX TMDS. Maqhubu a oache ea RX TMDS a tloha ho 25 MHz ho isa ho 340 MHz ha RX CDR bonyane ba oache ea litšupiso e le 50 MHz. IOPLL e sebelisoa ho hlahisa maqhubu a lioache a 5 bakeng sa oache ea TMDS lipakeng tsa 25 MHz ho isa ho 50 MHz le ho hlahisa maqhubu a oache a tšoanang bakeng sa oache ea TMDS lipakeng tsa 50 MHz - 340 MHz.
RX Transceiver Clock Out	rx_clk	Clock out e hlaphohetsoe ho transceiver, 'me maqhubu a fapana ho latela sekhahla sa data le bophara ba transceiver. RX transceiver clock out frequency = Sekhahla sa data ea Transceiver/ bophara ba Transceiver Bakeng sa sebopeho sena sa HDMI example, oache ea transceiver ea RX e tsoang kanaleng ea 1 e ts'oara oache ea litšupiso ea RX transceiver core (rx_coreclkin) le FRL IOPLL (pll_frl).

2.10. Lipontšo tsa Interface
Litafole li thathamisa matšoao a sebopeho sa HDMI example FRL e nolofalitsoe.
Lethathamo la 16. Lipontšo tsa boemo bo holimo

Letshwao	Tataiso	Bophara	Tlhaloso
Letšoao la Oscillator ka botong
clk_fpga_b3_p	Kenyeletso	1	100 MHz oache ea mahala e sebetsang bakeng sa oache ea mantlha ea litšupiso.
refclk4_p	Kenyeletso	1	100 MHz oache ea mahala e sebetsang bakeng sa oache ea referense ea transceiver.

Likonopo tsa Push ea Basebelisi le li-LED
mosebelisi_pb	Kenyeletso	3	Tobetsa konopo ho laola tšebetso ea moralo oa HDMI Intel FPGA IP.
cpu_resetn	Kenyeletso	1	Ho tsosolosa lefats'e.
user_led_g	Sephetho	8	Pontšo ea LED e tala. Sheba Ho hlophisoa ha Hardware leqepheng la 48 bakeng sa tlhaiso-leseling e batsi mabapi le mesebetsi ea LED.
user_dipsw	Kenyeletso	1	Phetoho ea DIP e hlalositsoeng ke mosebelisi. Sheba Ho hlophisoa ha Hardware leqepheng la 48 bakeng sa tlhaiso-leseling e batsi mabapi le mesebetsi ea switjha ea DIP.

HDMI FMC Morali oa Card Pins ho FMC Port B
fmcb_gbtclk_m2c_p_0	Kenyeletso	1	Oache ea HDMI RX TMDS.
fmcb_dp_m2c_p	Kenyeletso	4	Oache ea HDMI RX, liteishene tsa data tse khubelu, tse tala le tse putsoa.
fmcb_dp_c2m_p	Sephetho	4	Oache ea HDMI TX, liteishene tsa data tse khubelu, tse tala le tse putsoa.
fmcb_la_rx_p_9	Kenyeletso	1	Ho lemoha matla a HDMI RX +5V.
fmcb_la_rx_p_8	Sephetho	1	Sesebelisoa sa plug se chesang sa HDMI RX.
fmcb_la_rx_n_8	Kenyeletso	1	HDMI RX I2C SDA bakeng sa DDC le SCDC.
fmcb_la_tx_p_10	Kenyeletso	1	HDMI RX I2C SCL bakeng sa DDC le SCDC.
fmcb_la_tx_p_12	Kenyeletso	1	HDMI TX hot plug detect.
fmcb_la_tx_n_12	Kenyeletso	1	HDMI I2C SDA bakeng sa DDC le SCDC.
fmcb_la_rx_p_10	Kenyeletso	1	HDMI I2C SCL bakeng sa DDC le SCDC.
fmcb_la_tx_n_9	Kenyeletso	1	HDMI I2C SDA bakeng sa taolo ea ho khanna.
fmcb_la_rx_p_11	Kenyeletso	1	HDMI I2C SCL bakeng sa taolo ea ho khanna.
fmcb_la_tx_n_13	Sephetho	1	HDMI TX +5V Hlokomela: E fumaneha feela ha Phetolelo ea Karete ea Morali ea Bitec HDMI 9 e khethiloe.

Letlapa la 17. HDMI RX Lipontšo tsa Boemo bo Phahameng

Letshwao	Tataiso	Bophara	Tlhaloso
Oache le Seta Botjha Lipontšo
mgmt_clk	Kenyeletso	1	Kenyelletso ea oache ea sistimi (100 MHz).
tsosolosa	Kenyeletso	1	Ho kenya sistimi hape.
rx_tmds_clk	Kenyeletso	1	Oache ea HDMI RX TMDS.
i2c_clk	Kenyeletso	1	Kenyelletso ea oache bakeng sa sebopeho sa DDC le SCDC.

Oache le Seta Botjha Lipontšo
rxphy_cdr_refclk1	Kenyeletso	1	Kenyeletso ea oache bakeng sa oache ea referense ea RX CDR 1. Leqhubu la oache ke 100 MHz.
rx_vid_clk	Sephetho	1	Sephetho sa oache ea video.
sys_init	Sephetho	1	Ho qala tsamaiso ho tsosolosa tsamaiso ka mor'a ho matlafatsa.

RX Transceiver le IOPLL Lipontšo
rxpll_tmds_ notletsoe	Sephetho	1	E bontša hore oache ea TMDS IOPLL e notletsoe.
rxpll_frl_ notletsoe	Sephetho	1	E bontša hore oache ea FRL IOPLL e notletsoe.
rxphy_serial_data	Kenyeletso	4	Lintlha tsa seriale tsa HDMI ho RX Native PHY.
rxphy_ready	Sephetho	1	E bontša hore RX Native PHY e se e loketse.
rxphy_cal_busy_raw	Sephetho	4	RX Native PHY calibration e sebetsa ho transceiver arbiter.
rxphy_cal_busy_gated	Kenyeletso	4	Letšoao le phetheselang la ho lokisa ho tloha ho transceiver arbiter ho ea ho RX Native PHY.
rxphy_rcfg_slave_write	Kenyeletso	4	Transceiver reconfiguration Avalon memory-mapped interface ho tloha ho RX Native PHY ho ea ho transceiver arbiter.
rxphy_rcfg_slave_bala	Kenyeletso	4
rxphy_rcfg_lave_aterese	Kenyeletso	40
rxphy_rcfg_slave_writedata	Kenyeletso	128
rxphy_rcfg_slave_readdata	Sephetho	128
rxphy_rcfg_slave_waitrequest	Sephetho	4

Tsamaiso ea Reconfiguration ea RX
rxphy_rcfg_e phathahane	Sephetho	1	RX Reconfiguration lets'oao le phathahaneng.
rx_tmds_freq	Sephetho	24	Tekanyo ea maqhubu a oache ea HDMI RX TMDS (ka 10 ms).
rx_tmds_freq_valid	Sephetho	1	E bontša hore tekanyo ea maqhubu a oache ea RX TMDS e nepahetse.
rxphy_os	Sephetho	1	Ho fetaampling factor: •0: 1x oversampling • 1: 5× oversampling
rxphy_rcfg_master_write	Sephetho	1	Taolo ea ntlafatso ea RX Sehokelo sa memori sa Avalon ho transceiver arbiter.
rxphy_rcfg_master_read	Sephetho	1
rxphy_rcfg_master_aterese	Sephetho	12
rxphy_rcfg_master_writedata	Sephetho	32
rxphy_rcfg_master_readdata	Kenyeletso	32
rxphy_rcfg_master_waitrequest	Kenyeletso	1

Lipontšo tsa HDMI RX Core
rx_vid_clk_ notletsoe	Kenyeletso	1	E bontša hore vid_clk e tsitsitse.
rxcore_frl_rate	Sephetho	4	E bontša sekhahla sa FRL seo RX core e sebetsang ka sona. • 0: Mokhoa oa Lefa (TMDS) • 1: 3 Gbps 3 litsela • 2: 6 Gbps 4 litsela • 3: 6 Gbps 4 litsela • 4: 8 Gbps 4 litsela • 5: 10 Gbps 4 litsela • 6: 12 Gbps 4 litsela • 7-15: E bolokiloe
rxcore_frl_ notletsoe	Sephetho	4	Karolo e 'ngoe le e' ngoe e bonts'a tsela e ikhethileng e fihletseng senotlolo sa FRL. FRL e notletsoe ha RX core e sebetsa ka katleho ho lokisoa, deskew, le ho fihlela senotlolo sa lane. • Bakeng sa 3-lane mode, lane lock e finyelloa ha RX core e amohela Scrambler Reset (SR) kapa Start-Super-Block (SSB) bakeng sa linako tse ling le tse ling tse 680 FRL bakeng sa bonyane makhetlo a 3. • Bakeng sa 4-lane mode, lane lock e finyelloa ha RX core e amohela Scrambler Reset (SR) kapa Start-Super-Block (SSB) bakeng sa linako tse ling le tse ling tse 510 FRL bakeng sa bonyane makhetlo a 3.
rxcore_frl_ffe_levels	Sephetho	4	E tsamaellana le FFE_level bit ho SCDC 0x31 register bit [7:4] ho RX core.
rxcore_frl_flt_ready	Kenyeletso	1	Boikemisetso ba ho bonts'a RX e se e loketse hore ts'ebetso ea lihokelo e qale. Ha ho tiisitsoe, FLT_ready bit ho rejisetara ea SCDC 0x40 bit 6 le eona e tiisitsoe.
rxcore_frl_src_test_config	Kenyeletso	8	E totobatsa litlhophiso tsa tlhahlobo ea mohloli. Boleng bo ngotsoe ho SCDC Test Configuration rejisetara ho SCDC rejisetara 0x35.
rxcore_tbcr	Sephetho	1	E bonts'a karo-karolelano ea TMDS ho oache; e lumellana le ngoliso ea TMDS_Bit_Clock_Ratio bukeng ea SCDC 0x20 bit 1. • Ha o sebetsa ka mokhoa oa HDMI 2.0, karoloana ena ea tiisoa. E bonts'a tekanyo ea TMDS ho oache ea 40: 1. • Ha o sebetsa ka HDMI 1.4b, karoloana ena ha e tiisetsoe. E bonts'a karo-karolelano ea TMDS ho oache ea 10: 1. • Karoloana ena ha e sebelisoe molemong oa FRL.
rxcore_scrambler_enable	Sephetho	1	E bonts'a hore na data e amohetsoeng e hlakotsoe; e tsamaellana le lebala la Scrambling_Enable ho ngoliso ea SCDC 0x20 bit 0.
rxcore_audio_de	Sephetho	1	HDMI RX core audio interfaces Sheba ho Sink Interfaces karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
rxcore_audio_data	Sephetho	256
rxcore_audio_info_ai	Sephetho	48

rxcore_audio_N	Sephetho	20
rxcore_audio_CTS	Sephetho	20
rxcore_audio_metadata	Sephetho	165
rxcore_audio_format	Sephetho	5
rxcore_aux_pkt_data	Sephetho	72	HDMI RX ea mantlha ea li-interfaces tse thusang Sheba ho Sink Interfaces karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
rxcore_aux_pkt_addr	Sephetho	6
rxcore_aux_pkt_wr	Sephetho	1
rxcore_aux_data	Sephetho	72
rxcore_aux_sop	Sephetho	1
rxcore_aux_eop	Sephetho	1
rxcore_aux_valid	Sephetho	1
rxcore_aux_error	Sephetho	1
rxcore_gcp	Sephetho	6	Matšoao a mahlakoreng a mahlakoreng a HDMI RX Sheba ho Sink Interfaces karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
rxcore_info_avi	Sephetho	123
rxcore_info_vsi	Sephetho	61
rxcore_notletsoe	Sephetho	1	Likou tsa video tsa HDMI RX tsa mantlha Tlhokomeliso: N = lipikselse ka oache Sheba ho Sink Interfaces karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
rxcore_vid_data	Sephetho	N* 48
rxcore_vid_vsync	Sephetho	N
rxcore_vid_hsync	Sephetho	N
rxcore_vid_de	Sephetho	N
rxcore_vid_valid	Sephetho	1
rxcore_vid_lock	Sephetho	1
rxcore_mode	Sephetho	1	Taolo ea mantlha ea HDMI RX le likou tsa maemo. Tlhokomeliso: N = matšoao ka oache Sheba ho Sink Interfaces karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
rxcore_ctrl	Sephetho	N*6
rxcore_color_depth_sync	Sephetho	2
hdmi_5v_bona	Kenyeletso	1	HDMI RX 5V e lemoha le ho fumana hotplug. Sheba ho Sink Interfaces karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
HDmi_rx_hpd	Sephetho	1
rx_hpd_trigger	Kenyeletso	1

I2C Lipontšo
hdmi_rx_i2c_sda	Kenyeletso	1	HDMI RX DDC le SCDC segokanyimmediamentsi sa sebolokigolo.
hdmi_rx_i2c_scl	Kenyeletso	1

RX EDID RAM Lipontšo
edid_ram_access	Kenyeletso	1	Sehokelo sa phihlello sa HDMI RX EDID RAM.

edid_ram_aterese	Kenyeletso	8	Etsa bonnete ba hore edid_ram_access ha u batla ho ngola kapa ho bala ho tsoa ho EDID RAM, ho seng joalo lets'oao lena le lokela ho lula le le tlase. Ha o re edid_ram_access, hotplug signal desserts ho lumella ho ngola kapa ho balla EDID RAM. Ha phihlello ea RAM ea EDID e phethiloe, o lokela ho hlakola edid_ram_assess le liphatlalatso tsa lets'oao la hotplug. Mohloli o tla bala EDID e ncha ka lebaka la ho hotplug signal toggling.
edid_ram_write	Kenyeletso	1
edid_ram_bala	Kenyeletso	1
edid_ram_readdata	Sephetho	8
edid_ram_writedata	Kenyeletso	8
edid_ram_waitrequest	Sephetho	1

Lethathamo la 18.HDMI TX Lipontšo tsa Boemo bo Phahameng

Letshwao	Tataiso	Bophara	Tlhaloso
Oache le Seta Botjha Lipontšo
mgmt_clk	Kenyeletso	1	Kenyelletso ea oache ea sistimi (100 MHz).
tsosolosa	Kenyeletso	1	Ho kenya sistimi hape.
tx_tmds_clk	Kenyeletso	1	Oache ea HDMI RX TMDS.
txfpll_refclk1	Kenyeletso	1	Kenyelletso ea oache bakeng sa oache ea tšupiso ea TX PLL 1. Leqhubu la oache ke 100 MHz.
tx_vid_clk	Sephetho	1	Sephetho sa oache ea video.
tx_frl_clk	Sephetho	1	Tlhahiso ea oache ea FRL.
sys_init	Kenyeletso	1	Ho qala tsamaiso ho tsosolosa tsamaiso ka mor'a ho matlafatsa.
tx_init_etsa	Kenyeletso	1	Ho qala ha TX ho tsosolosa thibelo ea tsamaiso ea TX reconfiguration le transceiver reconfiguration interface.

TX Transceiver le IOPLL Lipontšo
txpll_frl_ notletsoe	Sephetho	1	E bonts'a oache ea lebelo la sehokelo mme oache ea FRL IOPLL e notletsoe.
txfpll_ notletsoe	Sephetho	1	E bontša hore TX PLL e notletsoe.
txphy_serial_data	Sephetho	4	Lintlha tsa seriale tsa HDMI ho tsoa ho TX Native PHY.
txphy_ready	Sephetho	1	E bontša hore TX Native PHY e se e loketse.
txphy_cal_ busy	Sephetho	1	TX Native PHY calibration lets'oao le sebetsang.
txphy_cal_busy_raw	Sephetho	4	Lets'oao le phetheselang la ho sebetsa ho transceiver arbiter.
txphy_cal_busy_gated	Kenyeletso	4	Letšoao le phetheselang la calibration ho tloha ho transceiver arbiter ho ea ho TX Native PHY.
txphy_rcfg_e phathahane	Sephetho	1	E bontša hore tokiso ea TX PHY e ntse e tsoela pele.
txphy_rcfg_slave_write	Kenyeletso	4	Transceiver reconfiguration Avalon memory-mapped interface ho tloha ho TX Native PHY ho ea ho transceiver arbiter.
txphy_rcfg_slave_bala	Kenyeletso	4
txphy_rcfg_slave_aterese	Kenyeletso	40
txphy_rcfg_slave_writedata Kenyeletso 128 txphy_rcfg_slave_readdata Sephetho 128 txphy_rcfg_slave_waitrequest Sephetho 4

TX Reconfiguration Management
tx_tmds_freq	Kenyeletso	24	boleng ba maqhubu a oache ea HDMI TX TMDS (ka 10 ms).
tx_os	Sephetho	2	Ho fetaampling factor: • 0: 1x oversampling • 1: 2× oversampling •2: 8x oversampling
txphy_rcfg_master_write	Sephetho	1	Tsamaiso ea TX reconfiguration Avalon memory-mapped interface ho transceiver arbiter.
txphy_rcfg_master_read	Sephetho	1
txphy_rcfg_master_address	Sephetho	12
txphy_rcfg_master_writedata	Sephetho	32
txphy_rcfg_master_readdata	Kenyeletso	32
txphy_rcfg_master_waitrequest	Kenyeletso	1
tx_reconfig_etsa	Sephetho	1	E bontša hore ts'ebetso ea TX reconfiguration e phethiloe.

Lipontšo tsa HDMI TX Core
tx_vid_clk_ notletsoe	Kenyeletso	1	E bontša hore vid_clk e tsitsitse.
txcore_ctrl	Kenyeletso	N*6	HDMI TX li-interface tsa taolo ea mantlha. Tlhokomeliso: N = lipikselse ka oache Sheba ho Lisebelisoa tsa Mohloli karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
txcore_mode	Kenyeletso	1
txcore_audio_de	Kenyeletso	1	HDMI TX li-interface tsa audio tsa mantlha. Sheba ho Lisebelisoa tsa Mohloli karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
txcore_audio_mute	Kenyeletso	1
txcore_audio_data	Kenyeletso	256
txcore_audio_info_ai	Kenyeletso	49
txcore_audio_N	Kenyeletso	20
txcore_audio_CTS	Kenyeletso	20
txcore_audio_metadata	Kenyeletso	166
txcore_audio_format	Kenyeletso	5
txcore_aux_ready	Sephetho	1	Lisebelisoa tsa mantlha tsa HDMI TX. Sheba ho Lisebelisoa tsa Mohloli karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
txcore_aux_data	Kenyeletso	72
txcore_aux_sop	Kenyeletso	1
txcore_aux_eop	Kenyeletso	1

txcore_aux_valid	Kenyeletso	1
txcore_gcp	Kenyeletso	6	Matšoao a mahlakoreng a mahlakoreng a HDMI TX. Sheba ho Lisebelisoa tsa Mohloli karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
txcore_info_avi	Kenyeletso	123
txcore_info_vsi	Kenyeletso	62
txcore_i2c_master_write	Kenyeletso	1	TX I2C master Avalon-mapped interface ho I2C master ka hare ho TX core. Hlokomela: Matshwao ana a fumaneha feela ha o bulela Kenyelletsa I2C paramethara.
txcore_i2c_master_read	Kenyeletso	1
txcore_i2c_master_address	Kenyeletso	4
txcore_i2c_master_writedata	Kenyeletso	32
txcore_i2c_master_readdata	Sephetho	32
txcore_vid_data	Kenyeletso	N* 48	Likou tsa video tsa HDMI TX tsa mantlha. Tlhokomeliso: N = lipikselse ka oacheRef er ho Lisebelisoa tsa Mohloli karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
txcore_vid_vsync	Kenyeletso	N
txcore_vid_hsync	Kenyeletso	N
txcore_vid_de	Kenyeletso	N
txcore_vid_ready	Sephetho	1
txcore_vid_overflow	Sephetho	1
txcore_vid_valid	Kenyeletso	1
txcore_frl_rate	Kenyeletso	4	Likhokahano tsa ngoliso ea SCDC.
txcore_frl_pattern	Kenyeletso	16
txcore_frl_start	Kenyeletso	1
txcore_scrambler_enable	Kenyeletso	1
txcore_tbcr	Kenyeletso	1

I2C Lipontšo
nios_tx_i2c_sda_in	Sephetho	1	TX I2C Master interface bakeng sa SCDC le DDC ho tloha ho processor ea Nios II ho ea ho buffer ea tlhahiso. Hlokomela: Haeba u bulela Kenyelletsa I2C parameter, matšoao ana a tla behoa ka hare ho TX core 'me a ke ke a bonahala boemong bona.
nios_tx_i2c_scl_in	Sephetho	1
nios_tx_i2c_sda_oe	Kenyeletso	1
nios_tx_i2c_scl_oe	Kenyeletso	1
nios_ti_i2c_sda_in	Sephetho	1	TX I2C Master interface ho tloha ho processor ea Nios II ho ea ho buffer ea tlhahiso ho laola redriver ea TI ho karete ea morali ea Bitec HDMI 2.1 FMC.
nios_ti_i2c_scl_in	Sephetho	1
nios_ti_i2c_sda_oe	Kenyeletso	1
nios_ti_i2c_scl_oe	Kenyeletso	1
hdmi_tx_i2c_sda	Kenyeletso	1	Khokahano ea TX I2C bakeng sa likhokahano tsa SCDC le DDC ho tloha ho buffer ho ea ho sehokelo sa HDMI TX.
hdmi_tx_i2c_scl	Kenyeletso	1
hdmi_tx_ti_i2c_sda	Kenyeletso	1	Khokahano ea TX I2C ho tloha ho buffer ea tlhahiso ho ea ho redriver ea TI ho karete ea morali ea Bitec HDMI 2.1 FMC.
hdmi_tx_ti_i2c_scl	Kenyeletso	1

tx_hpd_req	Sephetho	1	HDMI TX hotplug e lemoha li-interfaces.
hdmi_tx_hpd_n	Kenyeletso	1

Letlapa la 19. Lipontšo tsa Arbiter tsa Transceiver

Letshwao	Tataiso	Bophara	Tlhaloso
clk	Kenyeletso	1	Oache ea ho lokisa bocha. Oache ena e tlameha ho arolelana oache e ts'oanang le lithibelo tsa taolo ea tlhophiso.
tsosolosa	Kenyeletso	1	Seta lets'oao bocha. Reset ena e tlameha ho arolelana mokhoa o ts'oanang le li-block tsa taolo ea ntlafatso.
rx_rcfg_en	Kenyeletso	1	Reconfiguration ea RX e nolofalletsa lets'oao.
tx_rcfg_en	Kenyeletso	1	TX reconfiguration nolofalletsa letshwao.
rx_rcfg_ch	Kenyeletso	2	E bontša hore na ke mocha ofe o lokelang ho hlophisoa bocha mokokotlong oa RX. Letšoao lena le tlameha ho lula le tiile.
tx_rcfg_ch	Kenyeletso	2	E bontša hore na ke mocha ofe o lokelang ho hlophisoa bocha ho TX core. Letšoao lena le tlameha ho lula le tiile.
rx_reconfig_mgmt_write	Kenyeletso	1	Reconfiguration Avalon memory-mapped interfaces ho tswa ho RX reconfiguration management.
rx_reconfig_mgmt_read	Kenyeletso	1
rx_reconfig_mgmt_address	Kenyeletso	10
rx_reconfig_mgmt_writedata	Kenyeletso	32
rx_reconfig_mgmt_readdata	Sephetho	32
rx_reconfig_mgmt_waitrequest	Sephetho	1
tx_reconfig_mgmt_write	Kenyeletso	1	Reconfiguration Avalon memory-mapped interfaces ho tswa ho TX reconfiguration management.
tx_reconfig_mgmt_read	Kenyeletso	1
tx_reconfig_mgmt_address	Kenyeletso	10
tx_reconfig_mgmt_writedata	Kenyeletso	32
tx_reconfig_mgmt_readdata	Sephetho	32
tx_reconfig_mgmt_waitrequest	Sephetho	1
reconfig_write	Sephetho	1	Reconfiguration ea Avalon memory-mapped interfaces ho transceiver.
reconfig_bala	Sephetho	1
reconfig_aterese	Sephetho	10
reconfig_writedata	Sephetho	32
rx_reconfig_readdata	Kenyeletso	32
rx_reconfig_waitrequest	Kenyeletso	1
tx_reconfig_readdata	Kenyeletso	1
tx_reconfig_waitrequest	Kenyeletso	1

rx_cal_ busy	Kenyeletso	1	Letšoao la boemo ba ho lekanya ho tsoa ho transceiver ea RX.
tx_cal_ busy	Kenyeletso	1	Letšoao la boemo ba ho lekanya ho tsoa ho transceiver ea TX.
rx_reconfig_cal_busy	Sephetho	1	Letšoao la boemo ba ho lekanya ho RX transceiver PHY taolo ea ho seta bocha.
tx_reconfig_cal_busy	Sephetho	1	Letšoao la boemo ba ho lekanya ho tsoa ho TX transceiver PHY taolo ea ho seta bocha.

Letlapa la 20. RX-TX Link Signals

Letshwao	Tataiso	Bophara	Tlhaloso
video_clk	Kenyeletso	1	HDMI oache ea video.
rx_vid_lock	Kenyeletso	3	E bontša boemo ba senotlolo sa video sa HDMI RX.
rx_vid_valid	Kenyeletso	1	Lisebelisoa tsa video tsa HDMI RX.
rx_vid_de	Kenyeletso	N
rx_vid_hsync	Kenyeletso	N
rx_vid_vsync	Kenyeletso	N
rx_vid_data	Kenyeletso	N* 48
rx_aux_eop	Kenyeletso	1	Lisebelisoa tse thusang tsa HDMI RX.
rx_aux_sop	Kenyeletso	1
rx_aux_valid	Kenyeletso	1
rx_aux_data	Kenyeletso	72
tx_vid_de	Sephetho	N	Lisebelisoa tsa video tsa HDMI TX. Tlhokomeliso: N = lipikselse ka oache
tx_vid_hsync	Sephetho	N
tx_vid_vsync	Sephetho	N
tx_vid_data	Sephetho	N * 48
tx_vid_valid	Sephetho	1
tx_vid_ready	Kenyeletso	1
tx_aux_eop	Sephetho	1	Lisebelisoa tse thusang tsa HDMI TX.
tx_aux_sop	Sephetho	1
tx_aux_valid	Sephetho	1
tx_aux_data	Sephetho	72
tx_aux_ready	Kenyeletso	1

Letlapa la 21. Lipontšo tsa Tsamaiso ea Moqapi oa Sethala

Letshwao	Tataiso	Bophara	Tlhaloso
cpu_clk_in_clk_clk	Kenyeletso	1	CPU oache.
cpu_rst_in_reset_reset	Kenyeletso	1	CPU reset.

edid_ram_slave_translator_avalon_anti_slave_0_aterese	Sephetho	8	Li-interface tsa EDID RAM.
edid_ram_slave_translator_avalon_anti_slave_0_write	Sephetho	1
edid_ram_slave_translator_avalon_anti_slave_0_bala	Sephetho	1
edid_ram_slave_translator_avalon_anti_slave_0_readdata	Kenyeletso	8
edid_ram_slave_translator_avalon_anti_slave_0_writedata	Sephetho	8
edid_ram_slave_translator_avalon_anti_slave_0_waitrequest	Kenyeletso	1
hdmi_i2c_master_i2c_serial_sda_in	Kenyeletso	1	I2C Master interfaces ho tloha ho processor ea Nios II ho ea ho buffer ea tlhahiso bakeng sa taolo ea DDC le SCDC.
hdmi_i2c_master_i2c_serial_scl_in	Kenyeletso	1
hdmi_i2c_master_i2c_serial_sda_oe	Sephetho	1
hdmi_i2c_master_i2c_serial_scl_oe	Sephetho	1
redriver_i2c_master_i2c_serial_sda_in	Kenyeletso	1	I2C Master interfaces ho tloha ho processor ea Nios II ho ea ho buffer e hlahisoang bakeng sa tlhophiso ea TI redriver setting.
redriver_i2c_master_i2c_serial_scl_in	Kenyeletso	1
redriver_i2c_master_i2c_serial_sda_oe	Sephetho	1
redriver_i2c_master_i2c_serial_scl_oe	Sephetho	1
pio_in0_external_connection_export	Kenyeletso	32	Likarolo tse lumellanang tsa tlhahiso ea ho kenya. • Bit 0: E hokahane le lets'oao la user_dipsw ho laola mokhoa oa ho feta oa EDID. •Bit 1: Kopo ea TX HPD •Bit 2: transceiver ea TX e se e loketse •Bits 3: TX reconfiguration e entsoe •Bits 4–7: E bolokiloe • Bits 8–11: sekhahla sa RX FRL • Bit 12: RX TMDS bit clock ratio • Bits 13–16: RX FRL e notletsoe • Bits 17–20: Maemo a RX FFE • Bit 21: Tokiso ea RX e notletsoe

Letshwao	Tataiso	Bophara	Tlhaloso
			•Bit 22: Senotlolo sa video sa RX • Bit 23: Konopo ea 2 ea mosebedisi ho bala lirejisete tsa SCDC ho tloha sink e kantle •Bits 24–31: E bolokiloe
pio_out0_external_connection_export	Sephetho	32	Likarolo tse lumellanang tsa tlhahiso ea ho kenya. •Bit 0: TX HPD kananelo •Bit 1: Ho qalisoa ha TX ho entsoe • Bits 2–7: Behiloe • Bits 8–11: TX FRL reiti •Bits 12–27: TX FRL link training pattern • Bit 28: TX FRL qala • Bits 29–31: Behiloe
pio_out1_external_connection_export	Sephetho	32	Likarolo tse lumellanang tsa tlhahiso ea ho kenya. • Bit 0: phihlello ea RAM ea RX EDID • Bit 1: RX FLT e lokile • Bits 2–7: Behiloe • Bits 8–15: Tlhophiso ea tlhahlobo ea mohloli oa RX FRL •Bits 16–31: E bolokiloe

2.1. 1. Etsa li-Parameters tsa RTL
Sebelisa liparamente tsa HDMI TX le RX Top RTL ho etsa moralo oa example.
Boholo ba li-parameter tsa moralo li fumaneha ka har'a Moqapi Example tab ea HDMI Intel FPGA IP parameter editor. U ntse u ka fetola sebopeho sa example litlhophiso tseo u li entseng ho mohlophisi oa paramethara ka li-parameter tsa RTL.
Letlapa la 22. HDMI RX Top Parameters

Paramethara	Boleng	Tlhaloso
SUPPORT_DEEP_COLOR	• 0: Ha ho na 'mala o tebileng • : Mmala o tebileng	E khetha hore na mantlha a ka kenyelletsa lifomate tse tebileng tsa mebala.
TŠEPANG_MOTLATSI	• 0: Ha ho AUX •1: AUX	E etsa qeto hore na khouto ea kanale ea tlatsetso e kenyelelitsoe.
SYMBOLS_PER_CLOCK	8	E tšehetsa matšoao a 8 ka oache bakeng sa lisebelisoa tsa Intel Arria 10.
SUPPORT_AUDIO	• 0: Ha ho molumo • 1: Audio	E etsa qeto ea hore na mantlha a ka kenyelletsa molumo.

EDID_RAM_ADDR_WIDTH	8 (Boleng ba kamehla)	Log base 2 ea boholo ba RAM ea EDID.
BITEC_DAUGHTER_CARD_REV	• 0: Ha e lebise karete ea morali ea Bitec HDMI •4: E ts'ehetsa ntlafatso ea karete ea morali ea Bitec HDMI 4 • 6: Phetolelo ea karete ea morali ea Bitec HDMI 6 • 11: Targeting Bitec HDMI karete ea morali oa 11 (ea kamehla)	E totobatsa ntlafatso ea karete ea morali ea Bitec HDMI e sebelisitsoeng. Ha o fetola ntlafatso, moralo o ka fetola liteishene tsa transceiver mme oa khelosa polarity ho latela litlhoko tsa karete ea morali oa Bitec HDMI. Haeba u beha BITEC_DAUGHTER_CARD_REV parameter ho 0, moralo ha o etse liphetoho ho likanale tsa transceiver le polarity.
POLARITY_INVERSION	• 0: Fetola polarity • 1: Se ke oa khelosa polarity	Beha paramethara ena ho 1 ho fetola boleng ba karolo e 'ngoe le e 'ngoe ea data e kentsoeng. Ho beha paramethara ena ho 1 ho abela 4'b1111 koung ea rx_polinv ea transceiver ea RX.

Letlapa la 23. HDMI TX Top Parameters

Paramethara	Boleng	Tlhaloso
USE_FPLL	1	E ts'ehetsa fPLL joalo ka TX PLL bakeng sa lisebelisoa tsa Intel Arria 10 feela. Kamehla beha parameter ena ho 1.
SUPPORT_DEEP_COLOR	•0: Ha ho na 'mala o tebileng • 1: Mmala o tebileng	E khetha hore na mantlha a ka kenyelletsa lifomate tse tebileng tsa mebala.
TŠEPANG_MOTLATSI	• 0: Ha ho AUX • 1: AUX	E etsa qeto hore na khouto ea kanale ea tlatsetso e kenyelelitsoe.
SYMBOLS_PER_CLOCK	8	E tšehetsa matšoao a 8 ka oache bakeng sa lisebelisoa tsa Intel Arria 10.
SUPPORT_AUDIO	• 0: Ha ho molumo • 1: Audio	E etsa qeto ea hore na mantlha a ka kenyelletsa molumo.
BITEC_DAUGHTER_CARD_REV	• 0: Ha e lebise karete ea morali ea Bitec HDMI • 4: E tšehetsa ntlafatso ea karete ea morali ea Bitec HDMI 4 • 6: Targeting Bitec HDMI karete ea morali oa 6 • 11: Targeting Bitec HDMI karete ea morali oa 11 (ea kamehla)	E totobatsa ntlafatso ea karete ea morali ea Bitec HDMI e sebelisitsoeng. Ha o fetola ntlafatso, moralo o ka fetola liteishene tsa transceiver mme oa khelosa polarity ho latela litlhoko tsa karete ea morali oa Bitec HDMI. Haeba u beha BITEC_DAUGHTER_CARD_REV parameter ho 0, moralo ha o etse liphetoho ho likanale tsa transceiver le polarity.
POLARITY_INVERSION	• 0: Fetola polarity • 1: Se ke oa khelosa polarity	Beha paramethara ena ho 1 ho fetola boleng ba karolo e 'ngoe le e 'ngoe ea data e kentsoeng. Ho beha paramethara ena ho 1 ho abela 4'b1111 ho tx_polinv koung ea transceiver ea TX.

2.12. Setupo sa Hardware
Moqapi o nolofalitsoeng ke HDMI FRL exampe na le HDMI 2.1 e nang le bokhoni 'me e etsa pontšo ea loopthrough bakeng sa molapo o tloaelehileng oa video oa HDMI.
Ho etsa tlhahlobo ea hardware, hokela sesebelisoa se lumelletsoeng ke HDMI—joaloka karete ea litšoantšo e nang le sebopeho sa HDMI—ho kenya sink ea HDMI. Moqapi o tšehetsa mohloli le sink ea HDMI 2.1 kapa HDMI 2.0/1.4b.

1. Sink ea HDMI e khetholla boema-kepe hore e be molatsoana o tloaelehileng oa video ebe o e romella setsing sa ho khutlisa oache.
2. Mokotla oa HDMI RX o khetholla data ea video, e thusang, le ea molumo hore e khutlisetsoe morao ka ho bapa le konokono ea HDMI TX ka DCFIFO.
3. Boema-kepe ba mohloli oa HDMI oa karete ea morali oa FMC e fetisetsa setšoantšo ho sebali.

Hlokomela:
Haeba u batla ho sebelisa boto e 'ngoe ea ntlafatso ea Intel FPGA, u tlameha ho fetola likabelo tsa sesebelisoa le likabelo tsa phini. Setlhophiso sa analog ea transceiver se lekoa bakeng sa lisebelisoa tsa nts'etsopele tsa Intel Arria 10 FPGA le karete ea morali ea Bitec HDMI 2.1. U ka fetola li-setting tsa boto ea hau.
Letlapa la 24. Konopo ea Push ka Botong le Mesebetsi ea LED ea Mosebelisi

Tobetsa konopo / LED	Mosebetsi
cpu_resetn	Tobetsa hang ho etsa reset ea sistimi.
user_dipsw	Phetoho ea DIP e hlalositsoeng ke mosebelisi ho fetola mokhoa oa ho feta. •TLOA (boemo ba kamehla) = Ho feta HDMI RX ho FPGA e fumana EDID ho tloha siling ea kantle ebe e e hlahisa mohloling o kantle oo e hokahaneng le ona. • ON = O ka laola sekgahla se phahameng sa RX sa FRL ho tswa ho terminal ya Nios II. Taelo e fetola RX EDID ka ho laola boleng ba sekhahla sa FRL. Sheba ho Mathisa Moralo ka Litefiso tse Fapaneng tsa FRL leqepheng la 33 bakeng sa tlhaiso-leseling e batsi mabapi le ho beha litefiso tse fapaneng tsa FRL.
user_pb[0]	Tobetsa hang ho fetolela lets'oao la HPD mohloling o tloaelehileng oa HDMI.
user_pb[1]	Reserved.
user_pb[2]	Tobetsa hang ho bala mangolo a SCDC ho tloha sekoting se hokahaneng le TX ea karete ea morali ea Bitec HDMI 2.1 FMC. Hlokomela: Ho nolofalletsa ho bala, o tlameha ho seta DEBUG_MODE ho 1 ho software.
USER_LED[0]	Boemo ba senotlolo sa RX TMDS PLL. •0 = notletsoe • 1 = Notletsoe
USER_LED[1]	Boemo bo loketseng ba transceiver ea RX. •0 = Ha e a itokisetsa • 1 = Ho lokile
USER_LED[2]	RX sehokelo sa lebelo PLL, le video ea RX le boemo ba senotlolo sa FRL PLL. • 0 = E 'ngoe ea PLL ea oache ea RX e notletsoe • 1 = Ka bobeli li-PLL tsa oache ea RX li notletsoe
USER_LED[3]	Khokahano ea mantlha ea RX HDMI le boemo ba senotlolo sa deskew. • 0 = Bonyane kanale e le 1 e butswe • 1 = Dikanale tsohle di notletswe
USER_LED[4]	Boemo ba senotlolo sa video sa RX HDMI. • 0 = Notlolloa • 1 = Notletsoe
USER_LED[5]	PLL ea lebelo la khokahano ea TX, le video ea TX le boemo ba senotlolo sa FRL PLL. •0 = E 'ngoe ea PLL ea oache ea TX e notletsoe • 1 = Li-PLL tsa lioache tsa TX ka bobeli li notletsoe
USER_LED[6] USER_LED[7]	TX transceiver e loketse boemo. • 0 = Ha e a itokisetsa • 1 = Ho lokile Boemo ba koetliso ea khokahano ea TX. • 0 = E hlolehile • 1 = E fetile

2.13. Ketsiso Testbench
The simulation testbench e etsisa HDMI TX serial loopback ho ea mantlha ea RX.
Hlokomela:
Teko ena ea ketsiso ha e sebetse ho meralo e nang le paramethara ea Include I2C e lumelletsoeng.
Setšoantšo sa 19. HDMI Intel FPGA IP Simulation Testbench Block DiagramLetlapa la 25. Likarolo tsa Testbench

Karolo	Tlhaloso
TPG ea video	Jenereithara ea tlhahlobo ea video (TPG) e fana ka khothatso ea video.
Mohala S.ample Gen	Mantsoe a sampjenereithara e fana ka mamelwang sample stimulus. Jenereithara e hlahisa mokhoa o ntseng o eketseha oa data oa teko o tla fetisoa ka mocha oa molumo.
Aux Sample Gen	The aux sampjenereithara e fana ka thuso ea sample stimulus. Jenereithara e hlahisa data e tsitsitseng e lokelang ho fetisoa ho tloha ho transmitter.

Tlhahlobo ea CRC	Sehlahlobi sena se netefatsa hore na transceiver ea TX e fumaneng nako ea oache e lumellana le sekhahla sa data se lakatsehang.
Tlhahlobo ea Boitsebiso ba Audio	Tlhahlobo ea data ea molumo e bapisa hore na mohlala oa data oa tlhahlobo o ntseng o eketseha o amohetsoe le ho khethoa ka nepo.
Tlhahlobo ea data ea Aux	Tlhahlobo ea data ea aux e bapisa hore na data e lebelletsoeng ea aux e amohetsoe le ho khethoa ka nepo ka lehlakoreng la moamoheli.

HDMI simulation testbench e etsa liteko tse latelang tsa netefatso:

Tšobotsi ea HDMI	Netefatso
Lintlha tsa video	• Testbench e sebelisa CRC ho hlahloba video e kenang le e hlahisoang. • E lekola boleng ba CRC ba data e fetisitsoeng khahlano le CRC e baloang ho data e amohetsoeng ea video. • Testbench e ntan'o etsa tlhahlobo ka mor'a ho lemoha matšoao a 4 a tsitsitseng a V-SYNC ho tsoa ho moamoheli.
Lintlha tse thusang	• Taba sampjenereithara e hlahisa data e tsitsitseng e lokelang ho fetisoa ho tsoa ho transmitter. • Lehlakoreng la moamoheli, jenereithara e bapisa hore na data e thusang e lebelletsoeng e amohetsoe le ho hlalosoa ka nepo.
Lintlha tsa molumo	•Mantsoe a sampjenereithara e hlahisa mokhoa o ntseng o eketseha oa data oa tlhahlobo o lokelang ho fetisoa ka mocha oa molumo. • Ka lehlakoreng la moamoheli, sehlahlobi sa data sa mamelwang se hlahloba le ho bapisa hore na paterone ya data ya teko e ntseng e eketseha e amohetswe le ho hlakolwa ka nepo.

Ketsiso e atlehileng e qetella ka molaetsa o latelang:
# MATŠOAO_PER_CLOCK = 2
# VIC = 4
# FRL_RATE = 0
# BPP = 0
# AUDIO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Phatlalatso ea papali
Letlapa la 26. HDMI Intel FPGA IP Design Example Li-Silators tse tšehelitsoeng

Moetsisi	HDL ea boleng bo holimo	VHDL
ModelSim – Intel FPGA Edition/ ModelSim – Intel FPGA Starter Edition	Ee	Ee
VCS/VCS MX	Ee	Ee
Riviera-PRO	Ee	Ee
Xcelium Parallel	Ee	Che

2.14. Meeli ea Moralo
U hloka ho nahana ka mefokolo e itseng ha u tiisa sebopeho sa HDMI 2.1 example.

• TX ha e khone ho sebetsa ka mokhoa oa TMDS ha e le maemong a sa feteleng. Ho etsa teko ka mokhoa oa TMDS, fetola user_dipsw ho khutlela ho mokhoa oa ho feta.
• Motlakase oa Nios II o tlameha ho sebeletsa koetliso ea khokahano ea TX ho phetheloa ntle le tšitiso ea lits'ebetso tse ling.

2.15. Debugging Features
Moqapi ona example e fana ka likarolo tse itseng tsa debugging ho u thusa.
2.15.1. Software Debugging Molaetsa
U ka bulela molaetsa oa debugging ho software ho u fa thuso ea nako ea ho sebetsa.
Ho bulela molaetsa oa debugging ho software, latela mehato ena:

1. Fetola DEBUG_MODE ho 1 ho global.h script.
2. Matha script/build_sw.sh ho Nios II Command Shell.
3. Rulahanya bocha software/tx_control/tx_control.elf file ka ho tsamaisa taelo ho Nios II Command Shell:
   nios2-jarolla -r -g software/tx_control/tx_control.elf
4. Matha taelo ea terminal ea Nios II ho Nios II Command Shell:
   nios2-terminal

Ha o bulela molaetsa oa debugging, lintlha tse latelang li tla hatisa:

• Litlhophiso tsa redriver tsa TI ho TX le RX ka bobeli li baloa le ho hlahisoa hang ka mor'a lenaneo la ELF file.
• Molaetsa oa boemo bakeng sa tlhophiso ea RX EDID le ts'ebetso ea hotplug
• Qeto e nang le kapa ntle le tlhahisoleseling ea tšehetso ea FRL e ntšitsoeng ho EDID holim'a sinki e hokahaneng le TX. Lintlha tsena li hlahisoa bakeng sa hotplug e 'ngoe le e 'ngoe ea TX.
• Molaetsa oa boemo bakeng sa ts'ebetso ea koetliso ea khokahano ea TX nakong ea lithupelo tsa khokahano ea TX.

2.15.2. Lintlha tsa SCDC tse tsoang Sink e Hoketsoeng ho TX
U ka sebelisa sesebelisoa sena ho fumana lintlha tsa SCDC.

1. Sebelisa taelo ea "terminal" ea Nios II ho Nios II Command Shell: nios2-terminal
2. Tobetsa user_pb[2] ho lisebelisoa tsa ntlafatso tsa Intel Arria 10 FPGA.

Software e bala le ho bonts'a tlhahisoleseling ea SCDC sekoting se hokahaneng le TX ho terminal ea Nios II.
2.15.3. Tekanyo ea Maqhubu a Oache
Sebelisa tšobotsi ena ho lekola maqhubu a lioache tse fapaneng.

1. Ho hdmi_rx_top le hdmi_tx_top files, hlakisa maikutlo “//`define DEBUG_EN 1”.
2. Kenya lets'oao la refclock_measure ho tsoa ketsahalong e 'ngoe le e' ngoe ea mr_rate_detect ho Signal Tap Logic Analyzer ho fumana maqhubu a oache ea oache ka 'ngoe (ka nako ea 10 ms).
3. Kopanya moralo ka Signal Tap Logic Analyzer.
4. Lenaneo la SOF file 'me u tsamaise Signal Tap Logic Analyzer.

Lethathamo la 27. Lioache

Mojule	mr_rate_detect Boemo	Tshupanako e Lekanyetsoang
hdmi_rx_top	rx_pll_tmds	RX CDR oache 0
	rx_clk0_freq	Oache ea transceiver ea RX e tsoa ho kanale 0
	rx_vid_clk_freq	RX oache ea video
	rx_frl_clk_freq	Oache ea RX FRL
	rx_hsync_freq	Hsync frequency ea foreimi ea video e amoheloang
hdmi_tx_top	tx_clk0_freq	TX transceiver oache e tsoa ho kanale 0
	vid_clk_freq	Oache ea video ea TX
	frl_clk_freq	Oache ea TX FRL
	tx_hsync_freq	Hsync frequency ea foreimi ea video e lokelang ho fetisoa

2.16. Ho Ntlafatsa Moralo oa Hao
Letlapa la 28. HDMI Design Example Ho tsamaellana le Version e fetileng ea Intel Quartus Prime Pro Edition Software

Moqapi Example Variant	Bokhoni ba ho Ntlafatsa ho Intel Quartus Prime Pro Edition 20.3
HDMI 2.1 Moralo Example (Ts'ehetso FRL = 1)	Che

Bakeng sa moetso ofe kapa ofe o sa lumellaneng exampHo phaella moo, o lokela ho etsa se latelang:

1. Hlahisa sebopeho se secha sa example ho mofuta oa hajoale oa software oa Intel Quartus Prime Pro Edition o sebelisa meralo e tšoanang ea moralo oa hau o teng.
2. Bapisa moralo kaofela example directory e nang le sebopeho sa exampe hlahisitsoe ho sebelisoa mofuta oa software oa Intel Quartus Prime Pro Edition oa pejana. Koala liphetoho tse fumanoeng.

HDMI 2.0 Moralo Example (Ts'ehetso FRL = 0)

Moetso oa HDMI Intel FPGA IP example e bonts'a mohlala o le mong oa HDMI o ts'oanang oa loopback o nang le liteishene tse tharo tsa RX le liteishene tse 'ne tsa TX.
Letlapa la 29. HDMI Intel FPGA IP Design Example bakeng sa Intel Arria 10 Devices

Moqapi Example	Sekhahla sa Lintlha	Mokhoa oa Channel	Mofuta oa Loopback
Arria 10 HDMI RX-TX Retransmit	<6,000 Mbps	Simplex	E tsamaisana le FIFO buffer

Likaroloana

• Moralo ona o tiisa li-buffers tsa FIFO ho etsa phallo e tobileng ea video ea HDMI lipakeng tsa sink ea HDMI le mohloli.
  
• Moralo o sebelisa boemo ba LED bakeng sa ho lokisa liphoso tsa peletage.
• Moralo o tla le likhetho tsa RX le TX feela.
• Moralo o bonts'a ho kenngoa le ho sefa ha Dynamic Range and Mastering (HDR) InfoFrame ho mojule oa khokahanyo oa RX-TX.
• Moralo o bonts'a taolo ea phallo ea EDID ho tloha sekoting sa kantle sa HDMI ho ea mohloling oa kantle oa HDMI ha o hlohlelletsoa ke ketsahalo ea TX hot-plug.
• Moralo o lumella taolo ea nako ea ho matha ka sesebelisoa sa DIP le konopo ea push ho laola matšoao a mantlha a HDMI TX:
  — lets'oao la mode ho khetha foreimi ea video e kentsoeng ea DVI kapa HDMI
  — info_avi[47], info_vsi[61], le audio_info_ai [48] matšoao ho khetha phetisetso ea lipakete tse thusang ka mabanta a mahlakoreng kapa likoung tse thusang tsa data

Mohlala oa RX o fumana mohloli oa video ho tsoa ho jenereithara ea kantle ea video, 'me data ebe e feta ka loopback FIFO pele e fetisetsoa ho mohlala oa TX.
U hloka ho hokela sehlahlobi sa video sa kantle, monitor, kapa thelevishene e nang le khokahano ea HDMI ho mantlha ea TX ho netefatsa ts'ebetso.
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
Moetso oa HDMI 2.0 RX-TX oa ho fetisa sebopeho sa example e bonts'a loopback e ts'oanang ho mode ea simplex ea mocha oa HDMI Intel FPGA IP.
Setšoantšo sa 20. HDMI RX-TX Retransmit Block Diagram (Intel Quartus Prime Pro Edition)Setšoantšo sa 21. HDMI RX-TX Retransmit Block Diagram (Intel Quartus Prime Standard Edition)Lintlha Tse Amanang
Jitter of PLL Cascading kapa Non-Neilated Clock Path for Arria 10 PLL Reference Clock Sheba tharollo ena bakeng sa mosebetsi oa ho sebetsa haeba lioache tsa hau tsa moralo li na le ho eketsehileng.
jitter.
3.2. Litlhoko tsa Hardware le Software
Intel e sebelisa lisebelisoa tse latelang le software ho leka moralo oa example.
Lisebelisoa

• Intel Arria 10 GX FPGA Development Kit
• Mohloli oa HDMI (Yuniti ea processor ea Graphics (GPU))
• HDMI Sink (Monitor)
• Bitec HDMI FMC 2.0 karete ea morali (Revision 11)
• Lithapo tsa HDMI

Hlokomela:
U ka khetha ntlafatso ea karete ea morali oa Bitec HDMI ea hau. Beha boemo ba lehae BITEC_DAUGHTER_CARD_REV ho isa ho 4, 6, kapa 11 maemong a holimo file (a10_hdmi2_demo.v). Ha o fetola ntlafatso, moralo o ka fetola liteishene tsa transceiver mme oa khelosa polarity ho latela litlhoko tsa karete ea morali oa Bitec HDMI. Haeba u beha BITEC_DAUGHTER_CARD_REV parameter ho 0, moralo ha o etse liphetoho ho likanale tsa transceiver le polarity. Bakeng sa HDMI 2.1 moralo examples, tlas'a Moralo Example tab, seta Khatiso ea Karete ea Morali oa HDMI ho Revision 9, Revision 4, kapa ho se na karete ea morali. Boleng ba kamehla ke Revision 9.
Software

• Intel Quartus Prime version 18.1 le hamorao (bakeng sa tlhahlobo ea hardware)
• ModelSim – Intel FPGA Edition, ModelSim – Intel FPGA Starter Edition, , RivieraPRO, VCS (Verilog HDL only)/VCS MX, kapa Xcelium Parallel simulator

3.3. Sebopeho sa Directory
Li-directory li na le tse hlahisitsoeng files bakeng sa sebopeho sa HDMI Intel FPGA IP example.
Setšoantšo sa 22. Sebopeho sa Directory bakeng sa Moqapi ExampleLetlapa la 30. RTL e hlahisitsoeng Files

Liphutheli	Files
gxb	• /gxb_rx.qsys (Intel Quartus Prime Standard Edition) • /gxb_rx.ip (Intel Quartus Prime Pro Edition)
	• /gxb_rx_reset.qsys (Intel Quartus Prime Standard Edition) • /gxb_rx_reset.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx_fpll.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx_fpll.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx_reset.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx_reset.ip (Intel Quartus Prime Pro Edition)
hdmi_rx	•/hdmi_rx.qsys (Intel Quartus Prime Standard Edition) •/hdmi_rx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_rx_top.v
	/mr_clock_sync.v (Intel Quartus Prime Standard Edition)
	/mr_hdmi_rx_core_top.v (Intel Quartus Prime Standard Edition)
	/mr_rx_oversample.v (Intel Quartus Prime Standard Edition)
	/symbol_aligner.v
	Panasonic.hex (Intel Quartus Prime Pro Edition)
hdmi_tx	• /hdmi_tx.qsys (Intel Quartus Prime Standard Edition) •/hdmi_tx.ip (Intel Quartus Prime Pro Edition)

	/hdmi_tx_top.v
	/mr_ce.v (Intel Quartus Prime Standard Edition)
	/mr_hdmi_tx_core_top.v (Intel Quartus Prime Standard Edition)
	/mr_tx_oversample.v (Intel Quartus Prime Standard Edition)
i2c_master (Intel Quartus Prime Standard Edition)	/i2c_master_bit_ctrl.v
	/i2c_master_byte_ctrl.v
	/i2c_master_defines.v
	/i2c_master_top.v
	/oc_i2c_master.v
	/oc_i2c_master_hw.tcl
	/timescale.v
i2c_lekhoba	/edid_ram.qsys (Intel Quartus Prime Standard Edition)
	/Panasonic.hex (Intel Quartus Prime Standard Edition)
	/i2c_avl_mst_intf_gen.v
	/i2c_clk_cnt.v
	/i2c_condt_det.v
	/i2c_databuffer.v
	/i2c_rxshifter.v
	/i2c_slvfsm.v
	/i2c_spksuppp.v
	/i2c_txout.v
	/i2c_txshifter.v
	/i2cslave_to_avlmm_bridge.v
pll	• /pll_hdmi.qsys (Intel Quartus Prime Standard Edition) • /pll_hdmi.ip (Intel Quartus Prime Pro Edition)
	• /pll_hdmi_reconfig.qsys (Intel Quartus Prime Standard Edition) • /pll_hdmi_reconfig.ip (Intel Quartus Prime Pro Edition)
	quartus.ini
tloaelehileng	• /clock_control.qsys (Intel Quartus Prime Standard Edition) • /clock_control.ip (Intel Quartus Prime Pro Edition)
	• /fifo.qsys (Intel Quartus Prime Standard Edition) • /fifo.ip (Intel Quartus Prime Pro Edition)
	• /output_buf_i2c.qsys (Intel Quartus Prime Standard Edition) •/output_buf_i2c.ip (Intel Quartus Prime Pro Edition)
	/reset_controller.qsys (Intel Quartus Prime Standard Edition)
	/clock_crosser.v

	dcfifo_inst.v
	debouncer.sv (Intel Quartus Prime Pro Edition)
hdr	/altera_hdmi_aux_hdr.v
	/altera_hdmi_aux_snk.v
	/altera_hdmi_aux_src.v
	/altera_hdmi_hdr_infoframe.v
	/avalon_st_mutiplexer.qsys
reconfig_mgmt	/mr_compare_pll.v
	/mr_compare_rx.v
	/mr_rate_detect.v
	/mr_reconfig_master_pll.v
	/mr_reconfig_master_rx.v
	/mr_reconfig_mgmt.v
	/mr_rom_pll_dprioaddr.v
	/mr_rom_pll_valuemask_8bpc.v
	/mr_rom_pll_valuemask_10bpc.v
	/mr_rom_pll_valuemask_12bpc.v
	/mr_rom_pll_valuemask_16bpc.v
	/mr_rom_rx_dprioaddr_bitmask.v
	/mr_rom_rx_valuemask.v
	/mr_state_machine.v
sdc	/a10_hdmi2.sdc
	/mr_reconfig_mgmt.sdc
	/jtag.sdc
	/rxtx_link.sdc
	/mr_clock_sync.sdc (Intel Quartus Prime Standard Edition)

Lethathamo la 31. Ketsiso e hlahisitsoeng Files
Sheba karolo ea Simulation Testbench bakeng sa boitsebiso bo eketsehileng.

Liphutheli	Files
aldec	/aldec.do
	/rivierapro_setup.tcl
cadence	/cds.lib
	/hdl.var
	<cds_libs foldara>

motataisi	/mentor.etsa
	/msim_setup.tcl
li-synopsy	/vcs/filelenane.f
	/vcs/vcs_setup.sh
	/vcs/vcs_sim.sh
	/vcsmx/vcsmx_setup.sh
	/vcsmx/vcsmx_sim.sh
	/vcsmx/synopsys_sim_setup
xcelium (Khatiso ea Intel Quartus Prime Pro)	/cds.lib
	/hdl.var
	/xcelium_setup.sh
	/xcelium_sim.sh
tloaelehileng (Khatiso ea Intel Quartus Prime Pro)	/mohlala_files.tcl
	/riviera_files.tcl
	/vcs_files.tcl
	/vcsmx_files.tcl
	/xcelium_files.tcl
hdmi_rx	• /hdmi_rx.qsys (Intel Quartus Prime Standard Edition) • /hdmi_rx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_rx.sopcinfo (Intel Quartus Prime Standard Edition)
	/Panasonic.hex (Intel Quartus Prime Pro Edition)
	/symbol_aligner.v (Intel Quartus Prime Pro Edition)
hdmi_tx	• /hdmi_tx.qsys (Intel Quartus Prime Standard Edition) • /hdmi_tx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_tx.sopcinfo (Intel Quartus Prime Standard Edition)

Lethathamo la 32.E hlahisoang ke Software Files

Liphutheli	Files
tx_control_src Hlokomela: Foldara ea tx_control e boetse e na le tse kopitsoang tsa tsena files.	/intel_fpga_i2c.c (Intel Quartus Prime Pro Edition)
	/intel_fpga_i2c.h (Intel Quartus Prime Pro Edition)
	/i2c.c (Intel Quartus Prime Standard Edition)
	/i2c.h (Intel Quartus Prime Standard Edition)
	/main.c
	/xcvr_gpll_rcfg.c /xcvr_gpll_rcfg.h /ti_i2c.c (Intel Quartus Prime Standard Edition) /ti_i2c.h (Intel Quartus Prime Standard Edition)

3.4. Likarolo tsa Moqapi
Moetso oa HDMI Intel FPGA IP example hloka likarolo tsena.
Letlapa la 33. HDMI RX Top Components

Mojule	Tlhaloso
HDMI RX Core	IP e amohela lintlha tsa serial ho tsoa ho Transceiver Native PHY 'me e etsa ho hokahanya ha data, deskew ea kanal, decoding TMDS, decoding data decoding, video decoding, audio data decoding, and descrambling.
I2	I2C ke sebopeho se sebelisoang bakeng sa Sink Display Data Channel (DDC) le Status le Data Channel (SCDC). Mohloli oa HDMI o sebelisa DDC ho fumana bokhoni le litšobotsi tsa sink ka ho bala sebopeho sa data se Enhanced Extended Display Identification Data (E-EDID). • Liaterese tsa 8-bit I2C tsa makhoba tsa E-EDID ke 0xA0 le 0xA1. LSB e bontša mofuta oa phihlello: 1 bakeng sa ho bala le 0 bakeng sa ho ngola. Ha ketsahalo ea HPD e etsahala, lekhoba la I2C le arabela ho data ea E-EDID ka ho bala ho tsoa ho RAM ea on-chip. • Molaoli oa makhoba feela oa I2C o boetse o tšehetsa SCDC bakeng sa ts'ebetso ea HDMI 2.0. Aterese ea 8-bit I2C ea makhoba bakeng sa SCDC ke 0xA8 le 0xA9. Ha ketsahalo ea HPD e etsahala, lekhoba la I2C le etsa transaction ea ho ngola kapa ho bala ho tloha kapa ho tloha SCDC segokanyimmediamentsi sa sebolokigolo HDMI RX. Hlokomela: Taolo ena ea makhoba feela ea I2C bakeng sa SCDC ha e hlokehe haeba HDMI 2.0b e sa rereloa. Haeba u bulela Kenyelletsa I2C parameter, block ena e tla kenyelletsoa ka har'a mantlha mme e ke ke ea bonahala boemong bona.
EDID RAM	Moralo o boloka tlhahisoleseling ea EDID o sebelisa RAM 1-port IP core. Protocol e tloaelehileng ea terata e 'meli (oache le data) serial bus protocol (I2C-lekhoba-feela controller) e fetisetsa sebopeho sa data sa CEA-861-D Compliant E-EDID. EDID RAM ena e boloka lintlha tsa E-EDID. Hlokomela: Haeba u bulela Kenyelletsa EDID RAM parameter, block ena e tla kenyelletsoa ka har'a mantlha mme e ke ke ea bonahala boemong bona.
IOPLL	IOPLL e hlahisa oache ea litšupiso ea RX CDR, oache ea lebelo la sehokelo, le oache ea video bakeng sa oache e kenang ea TMDS. • Oache e hlahisoang ke 0 (CDR reference clock) • Oache e hlahisoang ke 1 (Hokahana oache ea lebelo) • Oache ea tlhahiso 2 (Oache ea video) Hlokomela: Tokiso ea kamehla ea IOPLL ha e sebetse bakeng sa qeto efe kapa efe ea HDMI. IOPLL e lokisoa bocha ho li-setting tse nepahetseng ha o matlafatsa.
Transceiver PHY Reset Controller	Transceiver PHY reset controller e netefatsa ts'ebetso e tšepahalang ea li-transceivers tsa RX. Tlhaloso ea ho tsosolosa ea molaoli enoa e bakoa ke ho tsosolosoa ha RX, 'me e hlahisa letšoao le lumellanang la analog le digital reset ho Transceiver Native PHY thibela ho ea ka tatellano ea ho tsosolosa ka hare ho thibela.
RX Native PHY	Hard transceiver block e amohelang data ea serial ho tsoa mohloling oa video o kantle. E senya data ea serial ho data e tšoanang pele e fetisetsa data ho HDMI RX core.
Tsamaiso ea Reconfiguration ea RX	Tsamaiso ea RX reconfiguration e sebelisang potoloho ea sekhahla sa ho lemoha le HDMI PLL ho khanna transceiver ea RX ho sebetsa ka litekanyetso leha e le life tsa khokahanyo ho tloha ho 250 Mbps ho ea ho 6,000 Mbps. Sheba setšoantšo sa 23 leqepheng la 63 ka tlase.

IOPLL Reconfiguration

IOPLL reconfiguration block e thusa ho hlophisa bocha ka nako ea nnete ea li-PLL ho Intel FPGAs. Sebaka sena se ntlafatsa maqhubu a oache ea tlhahiso le bandwidth ea PLL ka nako ea 'nete, ntle le ho lokisa FPGA kaofela. Sebaka sena se sebetsa ho 100 MHz ho lisebelisoa tsa Intel Arria 10. Ka lebaka la moeli oa tlhophiso ea IOPLL, sebelisa Quartus INI permit_nf_pll_reconfig_out_of_lock=on nakong ea IOPLL ea tlhahiso e ncha ea IP. Ho sebelisa Quartus INI, kenyelletsa "permit_nf_pll_reconfig_out_of_lock=on" ho quartus.ini file le sebaka ho file lethathamo la morero oa Intel Quartus Prime. U lokela ho bona molaetsa oa temoso ha u hlophisa "IOPLL reconfiguration block" (pll_hdmi_reconfig) ho software ea Quartus Prime e nang le INI. Hlokomela: Ntle le Quartus INI ena, IOPLL reconfiguration e ke ke ea phethoa haeba IOPLL e lahleheloa ke senotlolo nakong ea phetoho.

PIO

The parallel input/output (PIO) block e sebetsa e le taolo, boemo le ho reset interface ho ea kapa ho tsoa ho sub-system ea CPU.

Setšoantšo sa 23. Phallo ea Tatelano ea Mekhoa e Mengata ea Reconfiguration
Palo e bonts'a phallo ea tatellano ea li-reconfiguration tse ngata tsa molaoli ha a amohela phallo ea data e kentsoeng le maqhubu a oache ea litšupiso, kapa ha transceiver e notletsoe.Letlapa la 34. HDMI TX Top Components

Mojule	Tlhaloso
HDMI TX Core	IP ea mantlha e fumana data ea video ho tsoa boemong bo holimo mme e etsa encoding ea TMDS, encoding data encoding, audio data encoding, video data encoding, and scratching.
Monghali oa I2C	I2C ke sebopeho se sebelisoang bakeng sa Sink Display Data Channel (DDC) le Status le Data Channel (SCDC). Mohloli oa HDMI o sebelisa DDC ho fumana bokhoni le litšobotsi tsa sink ka ho bala sebopeho sa data se Enhanced Extended Display Identification Data (E-EDID). • Joaloka DDC, I2C Master e bala EDID ho tloha sekoting sa ka ntle ho lokisa boitsebiso ba EDID EDID RAM ho HDMI RX Top kapa bakeng sa ts'ebetso ea video. • Joaloka SCDC, I2C master e fetisetsa sebopeho sa data sa SCDC ho tloha mohloling oa FPGA ho ea ho teba ka ntle bakeng sa ts'ebetso ea HDMI 2.0b. Bakeng sa mohlalaample, haeba data e tsoang e le kaholimo ho 3,400 Mbps, processor ea Nios II e laela master ea I2C ho nchafatsa likotoana tsa TMDS_BIT_CLOCK_RATIO le SCRAMBLER_ENABLE tsa rejisetara ea tlhophiso ea sink SCDC ho 1.
IOPLL	IOPLL e fana ka oache ea lebelo la sehokelo le oache ea video ho tsoa ho oache e kenang ea TMDS. • Oache e hlahisoang ke 1 (Hokahana oache ea lebelo) • Oache ea tlhahiso 2 (Oache ea video) Hlokomela: Tokiso ea kamehla ea IOPLL ha e sebetse bakeng sa qeto efe kapa efe ea HDMI. IOPLL e lokisoa bocha ho li-setting tse nepahetseng ha o matlafatsa.
Transceiver PHY Reset Controller	Transceiver PHY reset controller e netefatsa ho qalisoa ho tšepahalang ha li-transceivers tsa TX. Kenyelletso ea ho tsosolosa ea molaoli enoa e hlahisoa ho tloha boemong bo phahameng, 'me e hlahisa letšoao le lumellanang la analog le digital reset ho Transceiver Native PHY thibela ho ea ka tatellano ea ho tsosolosa ka hare ho thibela. Letšoao la tlhahiso ea tx_ready ho tloha thibela ena e boetse e sebetsa e le pontšo ea ho tsosolosa HDMI Intel FPGA IP ho bontša hore transceiver e ntse e sebetsa, 'me e itokiselitse ho fumana data ho tloha bohareng.
Transceiver Native PHY	Hard transceiver block e amohelang data e ts'oanang ho tsoa ho mantlha ea HDMI TX mme e hlophisa data ho tsoa ho e fetisetsa. Sebopeho sa reconfiguration se nolofalitsoe ho TX Native PHY thibela ho bontša kamano pakeng tsa TX Native PHY le transceiver arbiter. Ha ho tlhophiso e ncha e etsoang bakeng sa TX Native PHY. Hlokomela: Ho kopana le tlhokeho ea HDMI TX inter-channel skew, beha khetho ea mokhoa oa TX bonding ho Intel Arria 10 Transceiver Native PHY parameter editor ho PMA le PCS tlamahano. U boetse u hloka ho eketsa tlhoko ea skew (set_max_skew) ho lets'oao la reset ea dijithale ho tsoa ho transceiver reset controller (tx_digitalreset) joalo ka ha ho khothalelitsoe ho Intel Arria 10 Transceiver PHY User Guide.
TX PLL	Transmitter PLL block e fana ka oache e potlakileng ea serial ho Transceiver Native PHY block. Bakeng sa sebopeho sena sa HDMI Intel FPGA IP example, fPLL e sebelisoa joalo ka TX PLL.
IOPLL Reconfiguration	IOPLL reconfiguration block e thusa ho hlophisa bocha ka nako ea nnete ea li-PLL ho Intel FPGAs. Sebaka sena se ntlafatsa maqhubu a oache ea tlhahiso le bandwidth ea PLL ka nako ea 'nete, ntle le ho lokisa FPGA kaofela. Sebaka sena se sebetsa ho 100 MHz ho lisebelisoa tsa Intel Arria 10. Ka lebaka la moeli oa tlhophiso ea IOPLL, sebelisa Quartus INI permit_nf_pll_reconfig_out_of_lock=on nakong ea IOPLL ea tlhahiso e ncha ea IP. Ho sebelisa Quartus INI, kenyelletsa "permit_nf_pll_reconfig_out_of_lock=on" ho quartus.ini file le sebaka ho file lethathamo la morero oa Intel Quartus Prime. U lokela ho bona molaetsa oa temoso ha u hlophisa "IOPLL reconfiguration block" (pll_hdmi_reconfig) ho Intel Quartus Prime software e nang le INI. Hlokomela: Ntle le Quartus INI ena, IOPLL reconfiguration e ke ke ea phethoa haeba IOPLL e lahleheloa ke senotlolo nakong ea phetoho.
PIO	The parallel input/output (PIO) block e sebetsa e le taolo, boemo le ho reset interface ho ea kapa ho tsoa ho sub-system ea CPU.

Letlapa la 35. Sekhahla sa Boitsebiso ba Transceiver le Oversampling Factor for E mong le e TMDS Clock Frequency Range

TMDS Clock Frequency (MHz)	Karolelano ea oache ea TMDS	Ho fetaampling Factor	Sekhahla sa Boitsebiso ba Transceiver (Mbps)
85–150	1	Ha e sebetse	3400–6000
100–340	0	Ha e sebetse	1000–3400
50–100	0	5	2500–5000
35–50	0	3	1050–1500
30–35	0	4	1200–1400
25–30	0	5	1250–1500

Lethathamo la 36. Li-blocks tse tloaelehileng tsa boemo bo holimo

Mojule

Tlhaloso

Transceiver Arbiter

Sebaka sena sa generic se thibelang li-transceivers ho tsosolosa ka nako e le 'ngoe ha li-transceivers tsa RX kapa TX ka har'a mocha o tšoanang oa' mele o hloka ho tsosolosoa. Ho tsosolosoa ha nako e le 'ngoe ho ama lits'ebetso moo li-transceivers tsa RX le TX ka har'a mocha o le mong li abeloang ho kenya ts'ebetsong e ikemetseng ea IP. Transceiver arbiter ena ke katoloso ea qeto e khothaletsoang bakeng sa ho kopanya simplex TX le simplex RX mocheng o tšoanang oa 'mele. Setsebi sena sa transceiver se boetse se thusa ho kopanya le ho rarolla likopo tsa Avalon-MM RX le TX tse lebisitsoeng ho li-transceivers tsa simplex RX le TX ka har'a mocha kaha boema-kepe ba sebopeho sa li-transceivers bo ka fihlelleha ka tatellano feela. Khokahano pakeng tsa transceiver arbiter le TX/RX Native PHY/PHY Reset Controller e thibela sebopeho sena sa khale.ample e bonts'a mokhoa oa generic o sebetsang bakeng sa motsoako ofe kapa ofe oa IP o sebelisang transceiver arbiter. Transceiver arbiter ha e hlokehe ha feela RX kapa TX transceiver e sebelisoa kanaleng. Transceiver arbiter e tsebahatsa mokopi oa tokiso bocha ka li-interface tsa eona tsa Avalon-MM mme e netefatsa hore tx_reconfig_cal_busy kapa rx_reconfig_cal_busy e tsamaellanang e kentsoe ka nepo. Bakeng sa sesebelisoa sa HDMI, ke RX feela e qalang ho hlophisa bocha. Ka ho tsamaisa kopo ea ntlafatso ea Avalon-MM ka mohanyetsi, mohanyetsi o tsebahatsa hore kopo ea ntlafatso e tsoa ho RX, eo joale e thibelang tx_reconfig_cal_busy ho tiisa le ho lumella rx_reconfig_cal_busy ho bolela. Keiti e thibela transceiver ea TX ho fallisetsoa mokhoeng oa ho lekanya e sa rera.

	Hlokomela: Hobane HDMI e hloka feela ho hlophisoa bocha ha RX, matšoao a tx_reconfig_mgmt_* a tlameletsoe. Hape, sebopeho sa Avalon-MM ha se hlokehe pakeng tsa arbiter le TX Native PHY block. Li-blocks li abeloa sebopeho sa sebopeho sa example ho bonts'a khokahanyo ea generic transceiver arbiter ho TX/RX Native PHY/PHY Reset Controller.
Sehokelo sa RX-TX	• Poelo ya data ya video le matshwao a kamahanyo ho tswa ho HDMI RX core loop ka DCFIFO ho phatlalla le dioache tsa video tsa RX le TX. • The General Control Packet (GCP), InfoFrames (AVI, VSI le AI), data e thusang, le audio data luop ka DCFIFOs mose ho RX le TX link tsa clock speed domains. • Boema-kepe bo thusang ba HDMI TX core bo laola lintlha tse thusang tse phallang ka DCFIFO ka khatello ea morao. The backpressure e tiisa hore ha ho na pakete e thusang e sa fellang boema-kepeng ba data bo thusang. • Sebaka sena se boetse se etsa sefa sa kantle: - E sefa data ea molumo le pakete ea nchafatso ea oache ea molumo ho tsoa mohloling oa data o thusang pele o fetisetsa koung ea data e thusang ea HDMI TX. Hlokomela: Ho tima sefa sena, tobetsa user_pb[2]. Lumella sefa sena ho netefatsa hore ha ho phetiso ea data ea molumo le sephutheloana sa nchafatso ea oache ea molumo molemong oa phetisetso ea tlatsetso ea data. - Filters the High Dynamic Range (HDR) InfoFrame ho tsoa ho HDMI RX data e thusang ebe e kenya ex.ample HDR InfoFrame ho data e thusang ea HDMI TX ka Avalon ST multiplexer.
CPU Sub-Sistimi	Sesebelisoa se senyenyane sa CPU se sebetsa joalo ka balaoli ba SCDC le DDC, le molaoli oa ntlafatso ea mohloli. • Mohloli oa taolo ea SCDC o na le I2C master controller. Mookameli ea hloahloa oa I2C o fetisetsa sebopeho sa data sa SCDC ho tloha mohloling oa FPGA ho ea sekoting sa kantle bakeng sa ts'ebetso ea HDMI 2.0b. Bakeng sa mohlalaample, haeba data e tsoang e le 6,000 Mbps, processor ea Nios II e laela molaoli ea ka sehloohong oa I2C ho nchafatsa likotoana tsa TMDS_BIT_CLOCK_RATIO le SCRAMBLER_ENABLE tsa rejisetere ea tlhophiso ea sink TMDS ho 1. • Monghali ea tšoanang oa I2C o boetse o fetisetsa sebopeho sa data sa DDC (E-EDID) pakeng tsa mohloli oa HDMI le sink e ka ntle. • Nios II CPU e sebetsa e le molaoli oa ho tsosolosa mohloli oa HDMI. CPU e ipapisitse le tlhahlobo ea sekhahla sa nako le nako ho tsoa mojuleng oa Tsamaiso ea Reconfiguration ea RX ho fumana hore na TX e hloka ho lokisoa bocha. Mofetoleli oa makhoba oa Avalon-MM o fana ka khokahano lipakeng tsa processor ea Nios II Avalon-MM master interface le li-interface tsa Avalon-MM tsa makhoba tsa IOPLL le TX Native PHY tse kentsoeng kantle. • Phallo ea tatellano ea ho hlophisa bocha bakeng sa TX e tšoana le RX, ntle le hore PLL le transceiver reconfiguration le tatellano ea ho tsosolosa e etsoa ka tatellano. Sheba setšoantšo sa 24 leqepheng la 67 .

Setšoantšo sa 24. Phallo ea Tatelano ea Reconfiguration
Palo e bonts'a phallo ea software ea Nios II e kenyelletsang taolo ea I2C master le HDMI mohloli.3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
Moetso oa HDMI Intel FPGA IP example kenyeletsa pontšo ea ho kenngoa ha HDR InfoFrame ho RX-TX loopback system.
HDMI Specification version 2.0b e lumella Dynamic Range le Mastering InfoFrame hore e fetisetsoe ka HDMI e thusang. Pontšong, "Axiliary Data Insertion block" e tšehetsa ho kenngoa ha HDR. U hloka feela ho fomata sephutheloana se reriloeng sa HDR InfoFrame joalo ka ha ho boletsoe tafoleng ea lethathamo la matšoao a module 'me u sebelise mojule oa AUX Insertion Control ho hlophisa ho kenngoa ha HDR InfoFrame hang ha foreimi e 'ngoe le e 'ngoe ea video.
Ho sena mohlalaample tlhophiso, maemong ao molapo o thusang o kenang o se o ntse o kenyelletsa HDR InfoFrame, litaba tsa HDR tse phatlalalitsoeng lia sefuoa. Sefa se qoba likhohlano tsa HDR InfoFrames hore li fetisoe mme e netefatsa hore ke litekanyetso tse boletsoeng feela ho HDR S.ample Data module li sebelisoa.
Setšoantšo sa 25. RX-TX Link le Dynamic Range le Mastering InfoFrame Insertion
Setšoantšo se bonts'a setšoantšo sa block sa sehokelo sa RX-TX se kenyelletsang Dynamic Range le Mastering InfoFrame ho kenyelletsoa ho molapo o thusang oa mantlha oa HDMI TX.
Letlapa la 37. Thibelo e Kenyellelitsoeng ea Boitsebiso (altera_hdmi_aux_hdr) Lipontšo

Letshwao	Tataiso	Bophara	Tlhaloso
Oache 'me Reset
clk	Kenyeletso	1	Kenyelletso ea oache. Oache ena e lokela ho hokahana le oache ea lebelo la sehokelo.
tsosolosa	Kenyeletso	1	Seta bocha.

Jenereithara ea Pakete e thusang le Lipontšo tsa Multiplexer
multiplexer_out_data	Sephetho	72	Phallo ea Avalon ho tsoa ho multiplexer.
multiplexer_out_valid	Sephetho	1
multiplexer_out_ready	Sephetho	1
multiplexer_out_startofpacket	Sephetho	1
multiplexer_out_endofpacket	Sephetho	1
multiplexer_out_channel	Sephetho	11
multiplexer_in_data	Kenyeletso	72	Kenyelletso ea Avalon ho boema-kepe ba In1 ea multiplexer. HDMI TX Video Vsync. Lets'oao lena le tlameha ho amahanngoa le sebaka sa marang-rang sa lebelo la sehokelo. Theko e kenya HDR InfoFrame ho molapo o thusang pheletsong e holimo ea lets'oao lena.
multiplexer_in_valid	Kenyeletso	1
multiplexer_in_ready	Kenyeletso	1
multiplexer_in_startofpacket	Kenyeletso	1
multiplexer_in_endofpacket hdmi_tx_vsync	Kenyeletso Kenyeletso	1 1

Lethathamo la 38. Lipontšo tsa HDR Data Module (altera_hdmi_hdr_infoframe)

Letshwao	Tataiso	Bophara	Tlhaloso
hb0	Sephetho	8	Header byte 0 ea Dynamic Range le Mastering InfoFrame: khoutu ea mofuta oa InfoFrame.
hb1	Sephetho	8	Header byte 1 ea Dynamic Range le Mastering InfoFrame: Nomoro ea mofuta oa InfoFrame.
hb2	Sephetho	8	Header byte 2 ea Dynamic Range le Mastering InfoFrame: Length of InfoFrame.
pb	Kenyeletso	224	Data byte ea Dynamic Range le Mastering InfoFrame.

Letlapa la 39. Dynamic Range le Mastering InfoFrame Data Byte Bundle Bit-Fields

Sebaka se senyenyane	Tlhaloso	Mofuta oa 1 oa Static Metadata
7:0	Data Byte 1: {5'h0, EOTF[2:0]}
15:8	Data Byte 2: {5'h0, Static_Metadata_Descriptor_ID[2:0]}
23:16	Data Byte 3: Static_Metadata_Descriptor	display_primaries_x[0], LSB
31:24	Data Byte 4: Static_Metadata_Descriptor	display_primaries_x[0], MSB
39:32	Data Byte 5: Static_Metadata_Descriptor	display_primaries_y[0], LSB
47:40	Data Byte 6: Static_Metadata_Descriptor	display_primaries_y[0], MSB
55:48	Data Byte 7: Static_Metadata_Descriptor	display_primaries_x[1], LSB
63:56	Data Byte 8: Static_Metadata_Descriptor	display_primaries_x[1], MSB
71:64	Data Byte 9: Static_Metadata_Descriptor	display_primaries_y[1], LSB
79:72	Data Byte 10: Static_Metadata_Descriptor	display_primaries_y[1], MSB
87:80	Data Byte 11: Static_Metadata_Descriptor	display_primaries_x[2], LSB
95:88	Data Byte 12: Static_Metadata_Descriptor	display_primaries_x[2], MSB
103:96	Data Byte 13: Static_Metadata_Descriptor	display_primaries_y[2], LSB
111:104	Data Byte 14: Static_Metadata_Descriptor	display_primaries_y[2], MSB
119:112	Data Byte 15: Static_Metadata_Descriptor	white_point_x, LSB
127:120	Data Byte 16: Static_Metadata_Descriptor	white_point_x, MSB
135:128	Data Byte 17: Static_Metadata_Descriptor	white_point_y, LSB

143:136	Data Byte 18: Static_Metadata_Descriptor	white_point_y, MSB
151:144	Data Byte 19: Static_Metadata_Descriptor	max_display_mastering_luminance, LSB
159:152	Data Byte 20: Static_Metadata_Descriptor	max_display_mastering_luminance, MSB
167:160	Data Byte 21: Static_Metadata_Descriptor	min_display_mastering_luminance, LSB
175:168	Data Byte 22: Static_Metadata_Descriptor	min_display_mastering_luminance, MSB
183:176	Data Byte 23: Static_Metadata_Descriptor	Boemo bo phahameng ba Leseli, LSB
191:184	Data Byte 24: Static_Metadata_Descriptor	Boemo bo phahameng ba Leseli la Boitsebiso, MSB
199:192	Data Byte 25: Static_Metadata_Descriptor	Boemo bo phahameng ba Frame-average Light Level, LSB
207:200	Data Byte 26: Static_Metadata_Descriptor	Maximum Frame-average Light Level, MSB
215:208	Reserved
223:216	Reserved

E thibela ho Kenya le ho Filtering ea HDR
Ho thibela ho kenya HDR le filthara ho u thusa ho netefatsa phetiso ea litaba tsa HDR tse seng li ntse li fumaneha mohloling o thusang ntle le phetoho ho RX-TX Retransmit design ex.ample.
Ho tima ho kenya le ho sefa HDR InfoFrame:

1. Beha block_ext_hdr_infoframe ho 1'b0 ho rxtx_link.v file ho thibela ho sefa ha HDR InfoFrame ho tsoa ho Auxiliary stream.
2. Beha multiplexer_in0_valid ea avalon_st_multiplexer ho altera_hdmi_aux_hdr.v file ho 1'b0 ho thibela Auxiliary Packet Generator ho theha le ho kenya HDR InfoFrame e eketsehileng ho TX Auxiliary stream.
   

3.6. Sekema sa ho Tlisa
Sekema sa oache se bonts'a libaka tsa oache ho HDMI Intel FPGA IP design example.
Setšoantšo sa 26. HDMI Intel FPGA IP Design ExampLe Clock Scheme (Intel Quartus Prime Pro Edition)Setšoantšo sa 27. HDMI Intel FPGA IP Design ExampLe Clock Scheme (Intel Quartus Prime Standard Edition)Letlapa la 40. Lipontšo tsa Scheme ea ho Tsupa

Tshupanako	Lebitso la Letshwao ka Moralo	Tlhaloso
TX IOPLL/ TX PLL Reference Clock 1	hdmi_clk_in	Oache ea litšupiso ho TX IOPLL le TX PLL. Leqhubu la oache le ts'oana le lebelo le lebelletsoeng la oache ea TMDS ho tsoa ho kanaleng ea oache ea HDMI TX TMDS. Bakeng sa sebopeho sena sa HDMI Intel FPGA IP example, oache ena e hokahane le oache ea RX TMDS ka sepheo sa pontšo. Ts'ebelisong ea hau, o hloka ho fana ka oache e inehetseng e nang le maqhubu a oache ea TMDS ho tsoa ho oscillator e ka khonehang bakeng sa ts'ebetso e ntle ea jitter. Hlokomela: Se ke oa sebelisa transceiver RX pin joalo ka oache ea litšupiso ea TX PLL. Moralo oa hau o tla hloleha ho lekana haeba o beha HDMI TX refclk ho phini ea RX.
TX Transceiver Clock Out	tx_clk	Clock out e hlaphohetsoe ho transceiver, 'me maqhubu a fapana ho latela sekhahla sa data le matšoao ka oache. TX transceiver clock out frequency = Sekhahla sa data ea Transceiver/ (Letšoao ka oache*10)
TX PLL Serial Clock	tx_bonding_clocks	Oache e potlakileng e hlahisoang ke TX PLL. Maqhubu a oache a behiloe ho ipapisitsoe le sekhahla sa data.
TX/RX Link Speed ​​Clock	ls_clk	Khokahano ea lebelo la oache. Lebelo la oache ea lebelo la sehokelo le ipapisitse le lebelo le lebelletsoeng la oache ea TMDS, oversampling factor, matšoao ka oache, le TMDS bit clock ratio.

		TMDS Bit Clock Karolelano	Khokahano ea Lebelo la Oache
		0	TMDS clock frequency/ Letshwao ka tshupanako
		1	Maqhubu a oache ea TMDS *4 / Letšoao ka oache
Oache ea video ea TX/RX	video_clk	Oache ea data ea video. Maqhubu a oache ea data ea video a tsoa ho sehokelo sa lebelo sa TX se ipapisitseng le botebo ba 'mala.
		TMDS Bit Clock Karolelano	Maqhubu a Clock ea Video
		0	TMDS clock/ Letshwao la tshupanako/ Boemo bo tebileng ba mmala
		1	Oache ea TMDS *4 / Letšoao ka oache/ Boemo bo tebileng ba 'mala
		Bits ka 'Mala	Ntlha ea botebo ba 'mala
		8	1
		10	1.25
		12	1.5
		16	2.0
Oache ea RX TMDS	tmds_clk_in	Kanane ea oache ea TMDS e tsoang ho HDMI RX mme e hokela oacheng ea litšupiso ho IOPLL.
RX CDR Reference Clock 0 /TX PLL Reference Clock 0	fr_clk	Oache e sebetsang ea mahala ho RX CDR le TX PLL. Oache ena ea hlokahala bakeng sa ho lekanya matla-up.
RX CDR Reference Clock 1	iopll_outclk0	Tshupanako ya RX CDR ya RX transceiver.
		Sekhahla sa Lintlha	RX Reference Clock Frequency
		Sekhahla sa data <1 Gbps	5× TMDS maqhubu a oache
		1 Gbps<Sekhahla sa data <3.4 Gbps	Leqhubu la oache ea TMDS
		Sekhahla sa data> 3.4 Gbps	4× TMDS maqhubu a oache
		• Sekhahla sa Lintlha <1 Gbps: Bakeng sa oversampling ho fihlela tlhoko e tlase ea sekhahla sa data ea transceiver. • Sekhahla sa Boitsebiso > 3.4 Gbps: Ho lefella sekhahla sa TMDS bit rate ho oache tekanyo ea 1/40 ho boloka sekhahla sa data ea transceiver ho tekanyo ea oache ho 1/10. Hlokomela: Se ke oa sebelisa transceiver RX pin joalo ka oache ea litšupiso ea CDR. Moralo oa hau o tla hloleha ho lekana haeba o beha HDMI RX refclk ho phini ea RX.
RX Transceiver Clock Out	rx_clk	Clock out e hlaphohetsoe ho transceiver, 'me maqhubu a fapana ho latela sekhahla sa data le matšoao ka oache. RX transceiver clock out frequency = Sekhahla sa data ea Transceiver/ (Letšoao ka oache*10)
Oache ea Tsamaiso	mgmt_clk	Oache ea mahala ea 100 MHz bakeng sa likarolo tsena:

		• Lihokelo tsa Avalon-MM bakeng sa ho hlophisoa bocha - Tlhokahalo ea maqhubu a maqhubu a pakeng tsa 100-125 MHz. •, PHY seta botjha taolo bakeng sa tatelano ya ho seta botjha ha transceiver - Lebelo la maqhubu a hlokahalang ke pakeng tsa 1-500 MHz. • IOPLL Reconfiguration - Nako e phahameng ea nako ea oache ke 100 MHz. • Reconfiguration ea RX bakeng sa tsamaiso • CPU • I2C Master
Clock ea I2C	i2c_clk	Kenyeletso ea oache ea 100 MHz e oacheng lekhoba la I2C, SCDC e ngolisang ho HDMI RX core, le EDID RAM.

Lintlha Tse Amanang

• Ho sebelisa Transceiver RX Pin joalo ka CDR Reference Clock
• Ho sebelisa Transceiver RX Pin joalo ka TX PLL Reference Clock

3.7. Lipontšo tsa Interface
Litafole li thathamisa matšoao a sebopeho sa HDMI Intel FPGA IP example.
Lethathamo la 41. Lipontšo tsa boemo bo holimo

Letshwao	Tataiso	Bophara	Tlhaloso
Letšoao la Oscillator ka botong
clk_fpga_b3_p	Kenyeletso	1	100 MHz oache ea mahala e sebetsang bakeng sa oache ea mantlha ea litšupiso
REFCLK_FMCB_P (Intel Quartus Prime Pro Edition)	Kenyeletso	1	Oache ea mahala ea 625 MHz bakeng sa oache ea referense ea transceiver; oache ena e ka ba ea maqhubu afe kapa afe

Likonopo tsa Push ea Basebelisi le li-LED
mosebelisi_pb	Kenyeletso	1	Tobetsa konopo ho laola tšebetso ea moralo oa HDMI Intel FPGA IP
cpu_resetn	Kenyeletso	1	Ho seta bocha lefatšeng ka bophara
user_led_g	Sephetho	4	Pontšo ea LED e tala Sheba ho Setupo sa Hardware leqepheng la 89 ho fumana lintlha tse ling mabapi le tšebetso ea LED.
user_led_r	Sephetho	4	Pontšo ea LED e khubelu Sheba ho Setupo sa Hardware leqepheng la 89 ho fumana lintlha tse ling mabapi le tšebetso ea LED.

HDMI FMC Morali oa Card Pins ho FMC Port B
fmcb_gbtclk_m2c_p_0	Kenyeletso	1	Oache ea HDMI RX TMDS
fmcb_dp_m2c_p	Kenyeletso	3	HDMI RX likanale tsa data tse khubelu, tse tala, le tse putsoa • Phetoho ea karete ea morali ea Bitec 11 — [0]: RX TMDS Channel 1 (Tala) — [1]: RX TMDS Channel 2 (Khubelu) — [2]: RX TMDS Channel 0 (Putsoa) • Phetoho ea karete ea morali ea Bitec 4 kapa 6 — [0]: RX TMDS Channel 1 (Tala)— polarity inverted — [1]: RX TMDS Channel 0 (Blue)— polarity inverted — [2]: RX TMDS Channel 2 (Khubelu)— polarity inverted
fmcb_dp_c2m_p	Sephetho	4	Oache ea HDMI TX, liteishene tsa data tse khubelu, tse tala le tse putsoa • Phetoho ea karete ea morali ea Bitec 11 — [0]: TX TMDS Channel 2 (Khubelu) — [1]: TX TMDS Channel 1 (Tala) — [2]: TX TMDS Channel 0 (Putsoa) — [3]: TX TMDS Clock Channel • Phetoho ea karete ea morali ea Bitec 4 kapa 6 — [0]: TX TMDS Clock Channel — [1]: TX TMDS Channel 0 (Putsoa) — [2]: TX TMDS Channel 1 (Tala) — [3]: TX TMDS Channel 2 (Khubelu)
fmcb_la_rx_p_9	Kenyeletso	1	Ho lemoha matla a HDMI RX +5V
fmcb_la_rx_p_8	Inout	1	Sesebelisoa sa plug se chesang sa HDMI RX
fmcb_la_rx_n_8	Inout	1	HDMI RX I2C SDA bakeng sa DDC le SCDC
fmcb_la_tx_p_10	Kenyeletso	1	HDMI RX I2C SCL bakeng sa DDC le SCDC
fmcb_la_tx_p_12	Kenyeletso	1	HDMI TX hot plug detect
fmcb_la_tx_n_12	Inout	1	HDMI I2C SDA bakeng sa DDC le SCDC
fmcb_la_rx_p_10	Inout	1	HDMI I2C SCL bakeng sa DDC le SCDC
fmcb_la_tx_p_11	Inout	1	HDMI I2C SDA bakeng sa taolo ea ho khanna
fmcb_la_rx_n_9	Inout	1	HDMI I2C SCL bakeng sa taolo ea ho khanna

Letlapa la 42. HDMI RX Lipontšo tsa Boemo bo Phahameng

Letshwao	Tataiso	Bophara	Tlhaloso
Oache le Seta Botjha Lipontšo
mgmt_clk	Kenyeletso	1	Kenyelletso ea oache ea sistimi (100 MHz)
fr_clk (Khatiso ea Intel Quartus Prime Pro)	Kenyeletso	1	Oache e sebetsang ea mahala (625 MHz) bakeng sa oache ea mantlha ea litšupiso tsa transceiver. Oache ena e ea hlokahala bakeng sa ho lekanya transceiver nakong ea ho phahamisa matla. Oache ena e ka ba ea maqhubu afe kapa afe.
tsosolosa	Kenyeletso	1	Ho kenya sistimi hape

Letshwao	Tataiso	Bophara	Tlhaloso
Oache le Seta Botjha Lipontšo
reset_xcvr_powerup (Intel Quartus Prime Pro Edition)	Kenyeletso	1	Transceiver reset input. Letšoao lena le tiisoa nakong ea ts'ebetso ea ho fetola lioache tsa litšupiso (ho tloha ho oache e sa lefelloeng ho ea ho oache ea TMDS) ha ho ntse ho phahama matla.
tmds_clk_in	Kenyeletso	1	Oache ea HDMI RX TMDS
i2c_clk	Kenyeletso	1	Kenyelletso ea oache bakeng sa sebopeho sa DDC le SCDC
video_clk_out	Sephetho	1	Sephetho sa oache ea video
ls_clk_out	Sephetho	1	Khokahano ea lebelo la oache
sys_init	Sephetho	1	Ho qala tsamaiso ho tsosolosa tsamaiso ka mor'a ho matlafatsa

RX Transceiver le IOPLL Lipontšo
rx_serial_data	Kenyeletso	3	Lintlha tsa seriale tsa HDMI ho RX Native PHY
gxb_rx_ready	Sephetho	1	E bontša hore RX Native PHY e se e loketse
gxb_rx_cal_busy_out	Sephetho	3	RX Native PHY calibration e sebetsa ho transceiver arbiter
gxb_rx_cal_busy_in	Kenyeletso	3	Letšoao le phetheselang la ho lokisa ho tloha ho transceiver arbiter ho ea ho RX Native PHY
iopll_e notletsoe	Sephetho	1	Bontša hore IOPLL e notletsoe
gxb_reconfig_write	Kenyeletso	3	Transceiver reconfiguration interface ea Avalon-MM ho tloha ho RX Native PHY ho ea ho transceiver arbiter.
gxb_reconfig_read	Kenyeletso	3
gxb_reconfig_aterese	Kenyeletso	30
gxb_reconfig_writedata	Kenyeletso	96
gxb_reconfig_readdata	Sephetho	96
gxb_reconfig_waitrequest	Sephetho	3

Tsamaiso ea Reconfiguration ea RX
rx_reconfig_en	Sephetho	1	RX Reconfiguration e nolofalletsa lets'oao
lekanya	Sephetho	24	Tekanyo ea maqhubu a oache ea HDMI RX TMDS (ka 10 ms)
tekanyo_e nepahetseng	Sephetho	1	E bontša hore letšoao la tekanyo le nepahetse
os	Sephetho	1	Ho fetaampling factor: • 0: Ha ho oversampling • 1: 5× oversampling
reconfig_mgmt_write	Sephetho	1	Taolo ea ntlafatso ea RX Sehokelo sa memori sa Avalon ho transceiver arbiter
reconfig_mgmt_read	Sephetho	1
reconfig_mgmt_address	Sephetho	12

reconfig_mgmt_writedata	Sephetho	32
reconfig_mgmt_readdata	Kenyeletso	32
reconfig_mgmt_waitrequest	Kenyeletso	1

Lipontšo tsa HDMI RX Core
TMDS_Bit_clock_Ratio	Sephetho	1	Likhokahano tsa ngoliso ea SCDC
audio_de	Sephetho	1	HDMI RX core audio interfaces Sheba karolo ea Sink Interfaces ho HDMI Intel FPGA IP User Guide bakeng sa boitsebiso bo eketsehileng.
audio_data	Sephetho	256
audio_info_ai	Sephetho	48
audio_N	Sephetho	20
audio_CTS	Sephetho	20
audio_metadata	Sephetho	165
audio_format	Sephetho	5
aux_pkt_data	Sephetho	72	HDMI RX ea mantlha ea li-interfaces tse thusang Sheba karolo ea Sink Interfaces ho HDMI Intel FPGA IP User Guide bakeng sa boitsebiso bo eketsehileng.
aux_pkt_addr	Sephetho	6
aux_pkt_wr	Sephetho	1
aux_data	Sephetho	72
aux_sop	Sephetho	1
aux_eop	Sephetho	1
aux_valid	Sephetho	1
aux_phoso	Sephetho	1
gcp	Sephetho	6	Matšoao a mahlakoreng a mahlakoreng a HDMI RX Sheba karolo ea Sink Interfaces ho HDMI Intel FPGA IP User Guide bakeng sa boitsebiso bo eketsehileng.
info_avi	Sephetho	112
info_vsi	Sephetho	61
colordepth_mgmt_sync	Sephetho	2
vid_data	Sephetho	N* 48	Likou tsa video tsa HDMI RX tsa mantlha Tlhokomeliso: N = matšoao ka oache Sheba ho Sink Interfaces karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
video_vsync	Sephetho	N
video_hsync	Sephetho	N
vid_de	Sephetho	N
mokgoa	Sephetho	1	Taolo ea mantlha ea HDMI RX le likou tsa maemo Tlhokomeliso: N = matšoao ka oache Sheba ho Sink Interfaces karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
ctrl	Sephetho	N*6
notletsoe	Sephetho	3
vid_lock	Sephetho	1
ka_5v_matla	Kenyeletso	1	HDMI RX 5V lemoha le hotplug detect Sheba ho Sink Interfaces karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
hdmi_rx_hpd_n	Inout	1

hdmi_rx_i2c_sda	Inout	1	HDMI RX DDC le SCDC segokanyimmediamentsi sa sebolokigolo
hdmi_rx_i2c_scl	Inout	1

RX EDID RAM Lipontšo
edid_ram_access	Kenyeletso	1	Sehokelo sa phihlello sa HDMI RX EDID RAM. Etsa bonnete ba hore edid_ram_access ha u batla ho ngola kapa ho bala ho tsoa ho EDID RAM, ho seng joalo lets'oao lena le lokela ho lula le le tlase.
edid_ram_aterese	Kenyeletso	8
edid_ram_write	Kenyeletso	1
edid_ram_bala	Kenyeletso	1
edid_ram_readdata	Sephetho	8
edid_ram_writedata	Kenyeletso	8
edid_ram_waitrequest	Sephetho	1

Letlapa la 43. HDMI TX Lipontšo tsa Boemo bo Phahameng

Letshwao	Tataiso	Bophara	Tlhaloso
Oache le Seta Botjha Lipontšo
mgmt_clk	Kenyeletso	1	Kenyelletso ea oache ea sistimi (100 MHz)
fr_clk (Khatiso ea Intel Quartus Prime Pro)	Kenyeletso	1	Oache e sebetsang ea mahala (625 MHz) bakeng sa oache ea mantlha ea litšupiso tsa transceiver. Oache ena e ea hlokahala bakeng sa ho lekanya transceiver nakong ea ho phahamisa matla. Oache ena e ka ba ea maqhubu afe kapa afe.
tsosolosa	Kenyeletso	1	Ho kenya sistimi hape
hdmi_clk_in	Kenyeletso	1	Oache ea litšupiso ho TX IOPLL le TX PLL. Maqhubu a oache a tšoana le a maqhubu a oache ea TMDS.
video_clk_out	Sephetho	1	Sephetho sa oache ea video
ls_clk_out	Sephetho	1	Khokahano ea lebelo la oache
sys_init	Sephetho	1	Ho qala tsamaiso ho tsosolosa tsamaiso ka mor'a ho matlafatsa
tsosolosa_xcvr	Kenyeletso	1	Khutlisetsa ho TX transceiver
reset_pll	Kenyeletso	1	Khutlisetsa ho IOPLL le TX PLL
reset_pll_reconfig	Sephetho	1	Khutlela ho tlhophiso bocha ea PLL

TX Transceiver le IOPLL Lipontšo
tx_serial_data	Sephetho	4	Lintlha tsa seriale tsa HDMI ho tsoa ho TX Native PHY
gxb_tx_ready	Sephetho	1	E bontša hore TX Native PHY e se e loketse
gxb_tx_cal_busy_out	Sephetho	4	TX Native PHY calibration lets'oao le phathahaneng ho transceiver arbiter
gxb_tx_cal_busy_in	Kenyeletso	4	Letšoao le phetheselang la calibration ho tloha ho transceiver arbiter ho ea ho TX Native PHY

TX Transceiver le IOPLL Lipontšo
iopll_e notletsoe	Sephetho	1	Bontša hore IOPLL e notletsoe
txpll_ notletsoe	Sephetho	1	Bontša hore TX PLL e notletsoe
gxb_reconfig_write	Kenyeletso	4	Transceiver reconfiguration Avalon memory-mapped interface ho tloha ho TX Native PHY ho ea ho transceiver arbiter.
gxb_reconfig_read	Kenyeletso	4
gxb_reconfig_aterese	Kenyeletso	40
gxb_reconfig_writedata	Kenyeletso	128
gxb_reconfig_readdata	Sephetho	128
gxb_reconfig_waitrequest	Sephetho	4

TX IOPLL le TX PLL Lipontšo tsa Reconfiguration
pll_reconfig_write/ tx_pll_reconfig_write	Kenyeletso	1	TX IOPLL/TX PLL reconfiguration Avalon memory-mapped interfaces
pll_reconfig_read/ tx_pll_reconfig_read	Kenyeletso	1
pll_reconfig_address/ tx_pll_reconfig_address	Kenyeletso	10
pll_reconfig_writedata/ tx_pll_reconfig_writedata	Kenyeletso	32
pll_reconfig_readdata/ tx_pll_reconfig_readdata	Sephetho	32
pll_reconfig_waitrequest/ tx_pll_reconfig_waitrequest	Sephetho	1
os	Kenyeletso	2	Ho fetaampling factor: • 0: Ha ho oversampling • 1: 3× oversampling • 2: 4× oversampling • 3: 5× oversampling
lekanya	Kenyeletso	24	E bonts'a maqhubu a oache ea TMDS ea qeto ea video e fetisang.

Lipontšo tsa HDMI TX Core
ctrl	Kenyeletso	6*N	HDMI TX core control interfaces Tlhokomeliso: N = Matshwao ka tshupanako Sheba karolo ea Source Interfaces ho HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
mokgoa	Kenyeletso	1
TMDS_Bit_clock_Ratio	Kenyeletso	1	SCLi-interface tsa DC register Sheba karolo ea Source Interfaces ho HDMI Intel FPGA IP User Guide bakeng sa boitsebiso bo eketsehileng.
Scrambler_Enable	Kenyeletso	1
audio_de	Kenyeletso	1	HDMI TX li-interface tsa audio tsa mantlha Sheba ho Lisebelisoa tsa Mohloli karolo ea HDMI Intel FPGA IP User Guide bakeng sa lintlha tse ling.
khutsufatso_ea molumo	Kenyeletso	1
audio_data	Kenyeletso	256
e tsoela pele…

Lipontšo tsa HDMI TX Core
audio_info_ai	Kenyeletso	49
audio_N	Kenyeletso	22
audio_CTS	Kenyeletso	22
audio_metadata	Kenyeletso	166
audio_format	Kenyeletso	5
i2c_master_write	Kenyeletso	1	TX I2C master Avalon-mapped interface ho I2C master ka hare ho TX core. Hlokomela: Matshwao ana a fumaneha feela ha o bulela Kenyelletsa I2C paramethara.
i2c_master_bala	Kenyeletso	1
i2c_master_aterese	Kenyeletso	4
i2c_master_writedata	Kenyeletso	32
i2c_master_readdata	Sephetho	32
aux_ready	Sephetho	1	Lisebelisoa tsa mantlha tsa HDMI TX Sheba karolo ea Source Interfaces ho HDMI Intel FPGA IP User Guide bakeng sa boitsebiso bo eketsehileng.
aux_data	Kenyeletso	72
aux_sop	Kenyeletso	1
aux_eop	Kenyeletso	1
aux_valid	Kenyeletso	1
gcp	Kenyeletso	6	Matšoao a mahlakoreng a mahlakoreng a HDMI TX Sheba karolo ea Source Interfaces ho HDMI Intel FPGA IP User Guide bakeng sa boitsebiso bo eketsehileng.
info_avi	Kenyeletso	113
info_vsi	Kenyeletso	62
vid_data	Kenyeletso	N* 48	Likou tsa video tsa HDMI TX tsa mantlha Tlhokomeliso: N = matšoao ka oache Sheba karolo ea Source Interfaces ho HDMI Intel FPGA IP User Guide bakeng sa boitsebiso bo eketsehileng.
video_vsync	Kenyeletso	N
video_hsync	Kenyeletso	N
vid_de	Kenyeletso	N

I2C le Hot Plug Fumana Lipontšo
nios_tx_i2c_sda_in (Intel Quartus Prime Pro Edition) Hlokomela: Ha u bulela file ea Kenyelletsa I2C parameter, letšoao lena le behiloe mokokotlong oa TX 'me le ke ke la bonahala boemong bona.	Sephetho	1	I2C Master Avalon e kentsoeng ka memori ea li-interfaces
nios_tx_i2c_scl_in (Intel Quartus Prime Pro Edition) Hlokomela: Ha u bulela file ea Kenyelletsa I2C parameter, letšoao lena le behiloe mokokotlong oa TX 'me le ke ke la bonahala boemong bona.	Sephetho	1
nios_tx_i2c_sda_oe (Intel Quartus Prime Pro Edition) Hlokomela: Ha u bulela file ea Kenyelletsa I2C parameter, letšoao lena le behiloe mokokotlong oa TX 'me le ke ke la bonahala boemong bona.	Kenyeletso	1
e tsoela pele…

I2C le Hot Plug Fumana Lipontšo
nios_tx_i2c_scl_oe (Intel Quartus Prime Pro Edition) Hlokomela: Ha u bulela file ea Kenyelletsa I2C parameter, letšoao lena le behiloe mokokotlong oa TX 'me le ke ke la bonahala boemong bona.	Kenyeletso	1
nios_ti_i2c_sda_in (Intel Quartus Prime Pro Edition)	Sephetho	1
nios_ti_i2c_scl_in (Intel Quartus Prime Pro Edition)	Sephetho	1
nios_ti_i2c_sda_oe (Intel Quartus Prime Pro Edition)	Kenyeletso	1
nios_ti_i2c_scl_oe (Intel Quartus Prime Pro Edition)	Kenyeletso	1
hdmi_tx_i2c_sda	Inout	1	HDMI TX DDC le SCDC interfaces
hdmi_tx_i2c_scl	Inout	1
hdmi_ti_i2c_sda (Intel Quartus Prime Pro Edition)	Inout	1	I2C interface bakeng sa Bitec Daughter Card Revision 11 TI181 Control
hdmi_tx_ti_i2c_sda (Intel Quartus Prime Standard Edition)	Inout	1
hdmi_ti_i2c_scl (Intel Quartus Prime Pro Edition)	Inout	1
hdmi_tx_ti_i2c_scl (Intel Quartus Prime Standard Edition)	Inout	1
tx_i2c_avalon_waitrequest	Sephetho	1	Khokahano ea memori ea Avalon ea master ea I2C
tx_i2c_avalon_address (Intel Quartus Prime Standard Edition)	Kenyeletso	3
tx_i2c_avalon_writedata (Intel Quartus Prime Standard Edition)	Kenyeletso	8
tx_i2c_avalon_readdata (Intel Quartus Prime Standard Edition)	Sephetho	8
tx_i2c_avalon_chipselect (Intel Quartus Prime Standard Edition)	Kenyeletso	1
tx_i2c_avalon_write (Intel Quartus Prime Standard Edition)	Kenyeletso	1
tx_i2c_irq (Intel Quartus Prime Standard Edition)	Sephetho	1
tx_ti_i2c_avalon_waitrequest (Intel Quartus Prime Standard Edition)	Sephetho	1
tx_ti_i2c_avalon_address (Intel Quartus Prime Standard Edition)	Kenyeletso	3
tx_ti_i2c_avalon_writedata (Intel Quartus Prime Standard Edition)	Kenyeletso	8
tx_ti_i2c_avalon_readdata (Intel Quartus Prime Standard Edition)	Sephetho	8
e tsoela pele…

I2C le Hot Plug Fumana Lipontšo
tx_ti_i2c_avalon_chipselect (Intel Quartus Prime Standard Edition)	Kenyeletso	1
tx_ti_i2c_avalon_write (Intel Quartus Prime Standard Edition)	Kenyeletso	1
tx_ti_i2c_irq (Intel Quartus Prime Standard Edition)	Sephetho	1
hdmi_tx_hpd_n	Kenyeletso	1	HDMI TX hotplug e lemoha li-interfaces
tx_hpd_ack	Kenyeletso	1
tx_hpd_req	Sephetho	1

Letlapa la 44. Lipontšo tsa Arbiter tsa Transceiver

Letshwao	Tataiso	Bophara	Tlhaloso
clk	Kenyeletso	1	Oache ea ho lokisa bocha. Oache ena e tlameha ho arolelana oache e ts'oanang le lithibelo tsa taolo ea tlhophiso.
tsosolosa	Kenyeletso	1	Seta lets'oao bocha. Reset ena e tlameha ho arolelana mokhoa o ts'oanang le li-block tsa taolo ea ntlafatso.
rx_rcfg_en	Kenyeletso	1	Reconfiguration ea RX e nolofalletsa lets'oao
tx_rcfg_en	Kenyeletso	1	TX reconfiguration nolofalletsa letshwao
rx_rcfg_ch	Kenyeletso	2	E bontša hore na ke mocha ofe o lokelang ho hlophisoa bocha mokokotlong oa RX. Letšoao lena le tlameha ho lula le tiile.
tx_rcfg_ch	Kenyeletso	2	E bontša hore na ke mocha ofe o lokelang ho hlophisoa bocha ho TX core. Letšoao lena le tlameha ho lula le tiile.
rx_reconfig_mgmt_write	Kenyeletso	1	Reconfiguration Avalon-MM interfaces ho tsoa ho RX reconfiguration management
rx_reconfig_mgmt_read	Kenyeletso	1
rx_reconfig_mgmt_address	Kenyeletso	10
rx_reconfig_mgmt_writedata	Kenyeletso	32
rx_reconfig_mgmt_readdata	Sephetho	32
rx_reconfig_mgmt_waitrequest	Sephetho	1
tx_reconfig_mgmt_write	Kenyeletso	1	Reconfiguration Avalon-MM interfaces ho tloha tsamaisong ea TX reconfiguration
tx_reconfig_mgmt_read	Kenyeletso	1
tx_reconfig_mgmt_address	Kenyeletso	10
tx_reconfig_mgmt_writedata	Kenyeletso	32
tx_reconfig_mgmt_readdata	Sephetho	32
tx_reconfig_mgmt_waitrequest	Sephetho	1
reconfig_write	Sephetho	1	Reconfiguration Avalon-MM interfaces ho transceiver
reconfig_bala	Sephetho	1
e tsoela pele…

Letshwao	Tataiso	Bophara	Tlhaloso
reconfig_aterese	Sephetho	10
reconfig_writedata	Sephetho	32
rx_reconfig_readdata	Kenyeletso	32
rx_reconfig_waitrequest	Kenyeletso	1
tx_reconfig_readdata	Kenyeletso	1
tx_reconfig_waitrequest	Kenyeletso	1
rx_cal_ busy	Kenyeletso	1	Letšoao la boemo ba ho lekanya ho tsoa ho transceiver ea RX
tx_cal_ busy	Kenyeletso	1	Letšoao la boemo ba ho lekanya ho tsoa ho transceiver ea TX
rx_reconfig_cal_busy	Sephetho	1	Letšoao la boemo ba ho lekanya ho RX transceiver PHY taolo ea ho seta bocha
tx_reconfig_cal_busy	Sephetho	1	Letšoao la boemo ba ho lekanya ho tsoa ho TX transceiver PHY taolo ea ho seta bocha

Letlapa la 45. RX-TX Link Signals

Letshwao	Tataiso	Bophara	Tlhaloso
tsosolosa	Kenyeletso	1	Khutlisa hape ho video/audio/e thusang/ mabanta a mahlakoreng a FIFO.
hdmi_tx_ls_clk	Kenyeletso	1	Oache ea lebelo ea khokahano ea HDMI TX
hdmi_rx_ls_clk	Kenyeletso	1	Oache ea lebelo ea khokahano ea HDMI RX
HDmi_tx_vid_clk	Kenyeletso	1	Oache ea video ea HDMI TX
HDmi_rx_vid_clk	Kenyeletso	1	Oache ea video ea HDMI RX
hdmi_rx_locked	Kenyeletso	3	E bonts'a boemo bo notletsoeng ba HDMI RX
hdmi_rx_de	Kenyeletso	N	Lisebelisoa tsa video tsa HDMI RX Tlhokomeliso: N = matšoao ka oache
hdmi_rx_hsync	Kenyeletso	N
hdmi_rx_vsync	Kenyeletso	N
hdmi_rx_data	Kenyeletso	N * 48
rx_audio_fomate	Kenyeletso	5	HDMI RX audio interfaces
rx_audio_metadata	Kenyeletso	165
rx_audio_info_ai	Kenyeletso	48
rx_audio_CTS	Kenyeletso	20
rx_audio_N	Kenyeletso	20
rx_audio_de	Kenyeletso	1
rx_audio_data	Kenyeletso	256
rx_gcp	Kenyeletso	6	Li-interface tsa HDMI RX tse lehlakoreng
rx_info_avi	Kenyeletso	112
rx_info_vsi	Kenyeletso	61
e tsoela pele…

Letshwao	Tataiso	Bophara	Tlhaloso
rx_aux_eop	Kenyeletso	1	Lisebelisoa tse thusang tsa HDMI RX
rx_aux_sop	Kenyeletso	1
rx_aux_valid	Kenyeletso	1
rx_aux_data	Kenyeletso	72
hdmi_tx_de	Sephetho	N	Lisebelisoa tsa video tsa HDMI TX Tlhokomeliso: N = matšoao ka oache
hdmi_tx_hsync	Sephetho	N
hdmi_tx_vsync	Sephetho	N
hdmi_tx_data	Sephetho	N * 48
tx_audio_fomate	Sephetho	5	Likhokahano tsa audio tsa HDMI TX
tx_audio_metadata	Sephetho	165
tx_audio_info_ai	Sephetho	48
tx_audio_CTS	Sephetho	20
tx_audio_N	Sephetho	20
tx_audio_de	Sephetho	1
tx_audio_data	Sephetho	256
tx_gcp	Sephetho	6	Li-interface tsa HDMI TX tse lehlakoreng
tx_info_avi	Sephetho	112
tx_info_vsi	Sephetho	61
tx_aux_eop	Sephetho	1	Lisebelisoa tse thusang tsa HDMI TX
tx_aux_sop	Sephetho	1
tx_aux_valid	Sephetho	1
tx_aux_data	Sephetho	72
tx_aux_ready	Sephetho	1

Letlapa la 46. Lipontšo tsa Tsamaiso ea Moqapi oa Sethala

Letshwao	Tataiso	Bophara	Tlhaloso
cpu_clk (Intel Quartus Prime Standard Edition)	Kenyeletso	1	CPU oache
clock_bridge_0_in_clk_clk (Intel Quartus Prime Pro Edition)
cpu_clk_reset_n (Intel Quartus Prime Standard Edition)	Kenyeletso	1	Puseletso ea CPU
reset_bridge_0_reset_reset_n (Intel Quartus Prime Pro Edition)
tmds_bit_clock_ratio_pio_external_connectio n_export	Kenyeletso	1	TMDS bit clock ratio
measure_pio_external_connection_export	Kenyeletso	24	Maqhubu a oache a TMDS a lebelletsoeng
e tsoela pele…

Letshwao	Tataiso	Bophara	Tlhaloso
measure_valid_pio_external_connection_expor t	Kenyeletso	1	E bontša hore PIO e nepahetse
i2c_master_i2c_serial_sda_in (Intel Quartus Prime Pro Edition)	Kenyeletso	1	I2C Master interfaces
i2c_master_i2c_serial_scl_in (Intel Quartus Prime Pro Edition)	Kenyeletso	1
i2c_master_i2c_serial_sda_oe (Intel Quartus Prime Pro Edition)	Sephetho	1
i2c_master_i2c_serial_scl_oe (Intel Quartus Prime Pro Edition)	Sephetho	1
i2c_master_ti_i2c_serial_sda_in (Intel Quartus Prime Pro Edition)	Kenyeletso	1
i2c_master_ti_i2c_serial_scl_in (Intel Quartus Prime Pro Edition)	Kenyeletso	1
i2c_master_ti_i2c_serial_sda_oe (Intel Quartus Prime Pro Edition)	Sephetho	1
i2c_master_ti_i2c_serial_scl_oe (Intel Quartus Prime Pro Edition)	Sephetho	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_address (Intel Quartus Prime Pro Edition)	Sephetho	3	I2C Master Avalon e nang le limmapa tsa memori tsa DDC le SCDC
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_write (Intel Quartus Prime Pro Edition)	Sephetho	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_readdata (Intel Quartus Prime Pro Edition)	Kenyeletso	32
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_writedata (Intel Quartus Prime Pro Edition)	Sephetho	32
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_waitrequest (Intel Quartus Prime Pro Edition)	Kenyeletso	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_chipselect (Intel Quartus Prime Pro Edition)	Sephetho	1
oc_i2c_master_ti_avalon_anti_slave_address (Intel Quartus Prime Standard Edition)	Sephetho	3	I2C Master Avalon-mapped interfaces bakeng sa Bitec morali oa phetolelo ea karete ea 11, taolo ea T1181
oc_i2c_master_ti_avalon_anti_slave_write (Intel Quartus Prime Standard Edition)	Sephetho	1
oc_i2c_master_ti_avalon_anti_slave_readdata (Intel Quartus Prime Standard Edition)	Kenyeletso	32
oc_i2c_master_ti_avalon_anti_slave_writedat a (Intel Quartus Prime Standard Edition)	Sephetho	32
oc_i2c_master_ti_avalon_anti_slave_waitrequ est (Intel Quartus Prime Standard Edition)	Kenyeletso	1
oc_i2c_master_ti_avalon_anti_slave_chipsele ct (Intel Quartus Prime Standard Edition)	Sephetho	1
e tsoela pele…

Letshwao	Tataiso	Bophara	Tlhaloso
edid_ram_access_pio_external_connection_exp ort	Sephetho	1	Li-interface tsa EDID RAM. Kopa edid_ram_access_pio_ external_connection_ export ha o batla ho ngolla kapa ho bala ho tsoa ho EDID RAM ka holimo ho RX. Hokela EDID RAM lekhoba la Avalon-MM ho Moqapi oa Platform ho sebopeho sa EDID RAM ho li-module tsa boemo bo holimo tsa RX.
edid_ram_slave_translator_aterese	Sephetho	8
edid_ram_slave_translator_write	Sephetho	1
edid_ram_slave_translator_read	Sephetho	1
edid_ram_slave_translator_readdata	Kenyeletso	8
edid_ram_slave_translator_writedata	Sephetho	8
edid_ram_slave_translator_waitrequest	Kenyeletso	1
powerup_cal_done_export (Intel Quartus Prime Pro Edition)	Kenyeletso	1	RX PMA Reconfiguration Avalon memory-mapped interfaces
rx_pma_cal_busy_export (Intel Quartus Prime Pro Edition)	Kenyeletso	1
rx_pma_ch_export (Intel Quartus Prime Pro Edition)	Sephetho	2
rx_pma_rcfg_mgmt_address (Intel Quartus Prime Pro Edition)	Sephetho	12
rx_pma_rcfg_mgmt_write (Intel Quartus Prime Pro Edition)	Sephetho	1
rx_pma_rcfg_mgmt_read (Intel Quartus Prime Pro Edition)	Sephetho	1
rx_pma_rcfg_mgmt_readdata (Intel Quartus Prime Pro Edition)	Kenyeletso	32
rx_pma_rcfg_mgmt_writedata (Intel Quartus Prime Pro Edition)	Sephetho	32
rx_pma_rcfg_mgmt_waitrequest (Intel Quartus Prime Pro Edition)	Kenyeletso	1
rx_pma_waitrequest_export (Intel Quartus Prime Pro Edition)	Kenyeletso	1
rx_rcfg_en_export (Intel Quartus Prime Pro Edition)	Sephetho	1
rx_rst_xcvr_export (Intel Quartus Prime Pro Edition)	Sephetho	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_waitrequest	Kenyeletso	1	TX PLL Reconfiguration Avalon memory-mapped interfaces
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_writedata	Sephetho	32
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_address	Sephetho	10
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_write	Sephetho	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_read	Sephetho	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_readdata	Kenyeletso	32
e tsoela pele…

Letshwao	Tataiso	Bophara	Tlhaloso
tx_pll_waitrequest_pio_external_connection_ thomello	Kenyeletso	1	TX PLL kopo ea ho emela
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_address	Sephetho	12	TX PMA Reconfiguration Avalon memory-mapped interfaces
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_write	Sephetho	1
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_read	Sephetho	1
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_readdata	Kenyeletso	32
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_writedata	Sephetho	32
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_waitrequest	Kenyeletso	1
tx_pma_waitrequest_pio_external_connection_ export	Kenyeletso	1	TX PMA kopo ea ho emela
tx_pma_cal_busy_pio_external_connection_exp ort	Kenyeletso	1	TX PMA Recalibration e phathahane
tx_pma_ch_export	Sephetho	2	Likanale tsa TX PMA
tx_rcfg_en_pio_external_connection_export	Sephetho	1	TX PMA Reconfiguration Noble
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_writedata	Sephetho	32	TX IOPLL Reconfiguration Avalon memory-mapped interfaces
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_readdata	Kenyeletso	32
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_waitrequest	Kenyeletso	1
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_address	Sephetho	9
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_write	Sephetho	1
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_read	Sephetho	1
tx_os_pio_external_connection_export	Sephetho	2	Ho fetaampling factor: • 0: Ha ho oversampling • 1: 3× oversampling • 2: 4× oversampling • 3: 5× oversampling
tx_rst_pll_pio_external_connection_export	Sephetho	1	Khutlisetsa ho IOPLL le TX PLL
tx_rst_xcvr_pio_external_connection_export	Sephetho	1	Khutlisetsa ho TX Native PHY
wd_timer_resetrequest_reset	Sephetho	1	Sebali sa nako ea ho lebela se hlophisitsoe bocha
color_depth_pio_external_connection_export	Kenyeletso	2	Botebo ba mmala
tx_hpd_ack_pio_external_connection_export	Sephetho	1	Bakeng sa TX hotplug lemoha ho tsukutlana ka matsoho
tx_hpd_req_pio_external_connection_export	Kenyeletso	1

3.8. Moralo RTL Parameters
Sebelisa liparamente tsa HDMI TX le RX Top RTL ho etsa moralo oa example.
Boholo ba liparamente tsa moralo li fumaneha ho Design Example tab ea HDMI Intel FPGA IP parameter editor. U ntse u ka fetola sebopeho sa example li-setting tsa hau
e entsoe ho mohlophisi oa paramethara ka li-parameter tsa RTL.

Letlapa la 47. HDMI RX Top Parameters

Paramethara	Boleng	Tlhaloso
SUPPORT_DEEP_COLOR	• 0: Ha ho na 'mala o tebileng • 1: Mmala o tebileng	E khetha hore na mantlha a ka kenyelletsa lifomate tse tebileng tsa mebala.
TŠEPANG_MOTLATSI	• 0: Ha ho AUX • 1: AUX	E etsa qeto hore na khouto ea kanale ea tlatsetso e kenyelelitsoe.
SYMBOLS_PER_CLOCK	8	E tšehetsa matšoao a 8 ka oache bakeng sa lisebelisoa tsa Intel Arria 10.
SUPPORT_AUDIO	• 0: Ha ho molumo • 1: Audio	E etsa qeto ea hore na mantlha a ka kenyelletsa molumo.
EDID_RAM_ADDR_WIDTH (Intel Quartus Prime Standard Edition)	8 (Boleng ba kamehla)	Log base 2 ea boholo ba RAM ea EDID.
BITEC_DAUGHTER_CARD_REV	• 0: Ha e lebise karete ea morali ea Bitec HDMI • 4: E tšehetsa ntlafatso ea karete ea morali ea Bitec HDMI 4 • 6: Targeting Bitec HDMI karete ea morali oa 6 •11: Targeting Bitec HDMI karete ea morali oa 11 (ea kamehla)	E totobatsa ntlafatso ea karete ea morali ea Bitec HDMI e sebelisitsoeng. Ha o fetola ntlafatso, moralo o ka fetola liteishene tsa transceiver mme oa khelosa polarity ho latela litlhoko tsa karete ea morali oa Bitec HDMI. Haeba u beha BITEC_DAUGHTER_CARD_REV parameter ho 0, moralo ha o etse liphetoho ho likanale tsa transceiver le polarity.
POLARITY_INVERSION	• 0: Fetola polarity • 1: Se ke oa khelosa polarity	Beha paramethara ena ho 1 ho fetola boleng ba karolo e 'ngoe le e 'ngoe ea data e kentsoeng. Ho beha paramethara ena ho 1 ho abela 4'b1111 koung ea rx_polinv ea transceiver ea RX.

Letlapa la 48. HDMI TX Top Parameters

Paramethara	Boleng	Tlhaloso
USE_FPLL	1	E ts'ehetsa fPLL joalo ka TX PLL feela bakeng sa lisebelisoa tsa Intel Cyclone® 10 GX. Kamehla beha parameter ena ho 1.
SUPPORT_DEEP_COLOR	• 0: Ha ho na 'mala o tebileng • 1: Mmala o tebileng	E khetha hore na mantlha a ka kenyelletsa lifomate tse tebileng tsa mebala.
TŠEPANG_MOTLATSI	• 0: Ha ho AUX • 1: AUX	E etsa qeto hore na khouto ea kanale ea tlatsetso e kenyelelitsoe.
SYMBOLS_PER_CLOCK	8	E tšehetsa matšoao a 8 ka oache bakeng sa lisebelisoa tsa Intel Arria 10.
e tsoela pele…

Paramethara	Boleng	Tlhaloso
SUPPORT_AUDIO	• 0: Ha ho molumo • 1: Audio	E etsa qeto ea hore na mantlha a ka kenyelletsa molumo.
BITEC_DAUGHTER_CARD_REV	• 0: Ha e lebise karete ea morali ea Bitec HDMI • 4: E tšehetsa ntlafatso ea karete ea morali ea Bitec HDMI 4 • 6: Targeting Bitec HDMI karete ea morali oa 6 • 11: Targeting Bitec HDMI karete ea morali oa 11 (ea kamehla)	E totobatsa ntlafatso ea karete ea morali ea Bitec HDMI e sebelisitsoeng. Ha o fetola ntlafatso, moralo o ka fetola liteishene tsa transceiver mme oa khelosa polarity ho latela litlhoko tsa karete ea morali oa Bitec HDMI. Haeba u beha BITEC_DAUGHTER_CARD_REV parameter ho 0, moralo ha o etse liphetoho ho likanale tsa transceiver le polarity.
POLARITY_INVERSION	• 0: Fetola polarity • 1: Se ke oa khelosa polarity	Beha paramethara ena ho 1 ho fetola boleng ba karolo e 'ngoe le e 'ngoe ea data e kentsoeng. Ho beha paramethara ena ho 1 ho abela 4'b1111 ho tx_polinv koung ea transceiver ea TX.

3.9. Setupo sa Hardware
Moetso oa HDMI Intel FPGA IP exampe na le HDMI 2.0b e nang le bokhoni 'me e etsa pontšo ea loopthrough bakeng sa molapo o tloaelehileng oa video oa HDMI.
Ho etsa tlhahlobo ea hardware, hokela sesebelisoa se lumelletsoeng ke HDMI-joalo ka karete ea litšoantšo e nang le sebopeho sa HDMI-ho block ea Transceiver Native PHY RX, le sink ea HDMI.
kenya letsoho.

1. Sink ea HDMI e khetholla boema-kepe hore e be molatsoana o tloaelehileng oa video ebe o e romella setsing sa ho khutlisa oache.
2. Mokotla oa HDMI RX o khetholla data ea video, e thusang, le ea molumo hore e khutlisetsoe morao ka ho bapa le konokono ea HDMI TX ka DCFIFO.
3. Boema-kepe ba mohloli oa HDMI oa karete ea morali oa FMC e fetisetsa setšoantšo ho sebali.

Hlokomela:
Haeba u batla ho sebelisa boto e 'ngoe ea ntlafatso ea Intel FPGA, u tlameha ho fetola likabelo tsa sesebelisoa le likabelo tsa phini. Setlhophiso sa analog ea transceiver se lekoa bakeng sa lisebelisoa tsa nts'etsopele tsa Intel Arria 10 FPGA le karete ea morali ea Bitec HDMI 2.0. U ka fetola li-setting tsa boto ea hau.

Letlapa la 49. Konopo ea Push ka Botong le Mesebetsi ea LED ea Mosebelisi

Tobetsa konopo / LED	Mosebetsi
cpu_resetn	Tobetsa hang ho etsa reset ea sistimi.
user_pb[0]	Tobetsa hang ho fetolela lets'oao la HPD mohloling o tloaelehileng oa HDMI.
user_pb[1]	• Tobetsa o hatelle ho laela TX core ho romela letshwao la khouto ya DVI. • E lokolle ho romela letshwao la khouto ya HDMI.
user_pb[2]	• Tobetsa o hatelle ho laela TX core ho emisa ho romela InfoFrames ho tsoa matshwaong a sehlopha se ka thoko. • Lokolla ho tswella pele ho romela InfoFrames ho tswa matshwaong a sehlopha se ka thoko.
USER_LED[0]	Boemo ba senotlolo sa RX HDMI PLL. • 0 = Notlolloa • 1 = Notletsoe
USER_LED[1]	Boemo bo loketseng ba transceiver ea RX.
e tsoela pele…

Tobetsa konopo / LED	Mosebetsi
	• 0 = Ha e a itokisetsa • 1 = Ho lokile
USER_LED[2]	Boemo ba senotlolo sa mantlha sa RX HDMI. • 0 = Bonyane kanale e le nngwe e butswe • 1 = Likanale tse 3 kaofela li notletsoe
USER_LED[3]	RX e fetangampboemo ba ling. • 0 = Tse sa fetengampled (sekhahla sa data> 1,000 Mbps ho sesebelisoa sa Intel Arria 10) • 1 = Oversampled (sekhahla sa data <100 Mbps ho sesebelisoa sa Intel Arria 10)
USER_LED[4]	Boemo ba senotlolo sa TX HDMI PLL. • 0 = Notlolloa • 1 = Notletsoe
USER_LED[5]	TX transceiver e loketse boemo. • 0 = Ha e a itokisetsa • 1 = Ho lokile
USER_LED[6]	Boemo ba senotlolo sa TX transceiver PLL. • 0 = Notlolloa • 1 = Notletsoe
USER_LED[7]	TX tse fetangampboemo ba ling. • 0 = Tse sa fetengampled (sekhahla sa data> 1,000 Mbps ho sesebelisoa sa Intel Arria 10) • 1 = Oversampled (sekhahla sa data <1,000 Mbps ho sesebelisoa sa Intel Arria 10)

3.10. Ketsiso Testbench
The simulation testbench e etsisa HDMI TX serial loopback ho ea mantlha ea RX.
Hlokomela:
Teko ena ea ketsiso ha e sebetse ho meralo e nang le paramethara ea Include I2C e lumelletsoeng.

3. HDMI 2.0 Moralo Example (Ts'ehetso FRL = 0)
683156 | 2022.12.27
Setšoantšo sa 28. HDMI Intel FPGA IP Simulation Testbench Block Diagram

Letlapa la 50. Likarolo tsa Testbench

Karolo	Tlhaloso
TPG ea video	Jenereithara ea tlhahlobo ea video (TPG) e fana ka khothatso ea video.
Mohala S.ample Gen	Mantsoe a sampjenereithara e fana ka mamelwang sample stimulus. Jenereithara e hlahisa mokhoa o ntseng o eketseha oa data oa teko o tla fetisoa ka mocha oa molumo.
Aux Sample Gen	The aux sampjenereithara e fana ka thuso ea sample stimulus. Jenereithara e hlahisa data e tsitsitseng e lokelang ho fetisoa ho tloha ho transmitter.
Tlhahlobo ea CRC	Sehlahlobi sena se netefatsa hore na transceiver ea TX e fumaneng nako ea oache e lumellana le sekhahla sa data se lakatsehang.
Tlhahlobo ea Boitsebiso ba Audio	Tlhahlobo ea data ea molumo e bapisa hore na mohlala oa data oa tlhahlobo o ntseng o eketseha o amohetsoe le ho khethoa ka nepo.
Tlhahlobo ea data ea Aux	Tlhahlobo ea data ea aux e bapisa hore na data e lebelletsoeng ea aux e amohetsoe le ho khethoa ka nepo ka lehlakoreng la moamoheli.

HDMI simulation testbench e etsa liteko tse latelang tsa netefatso:

Tšobotsi ea HDMI	Netefatso
Lintlha tsa video	• Testbench e sebelisa CRC ho hlahloba video e kenang le e hlahisoang. • E lekola boleng ba CRC ba data e fetisitsoeng khahlano le CRC e baloang ho data e amohetsoeng ea video. • Testbench e ntan'o etsa tlhahlobo ka mor'a ho lemoha matšoao a 4 a tsitsitseng a V-SYNC ho tsoa ho moamoheli.
Lintlha tse thusang	• Taba sampjenereithara e hlahisa data e tsitsitseng e lokelang ho fetisoa ho tsoa ho transmitter. • Lehlakoreng la moamoheli, jenereithara e bapisa hore na data e thusang e lebelletsoeng e amohetsoe le ho hlalosoa ka nepo.
Lintlha tsa molumo	• Mantswe a mamelwang sampjenereithara e hlahisa mokhoa o ntseng o eketseha oa data oa tlhahlobo o lokelang ho fetisoa ka mocha oa molumo. • Ka lehlakoreng la moamoheli, sehlahlobi sa data sa mamelwang se hlahloba le ho bapisa hore na paterone ya data ya teko e ntseng e eketseha e amohetswe le ho hlakolwa ka nepo.

Ketsiso e atlehileng e qetella ka molaetsa o latelang:
# MATŠOAO_PER_CLOCK = 2
# VIC = 4
# FRL_RATE = 0
# BPP = 0
# AUDIO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Phatlalatso ea papali

Letlapa la 51. HDMI Intel FPGA IP Design Example Li-Silators tse tšehelitsoeng

Moetsisi	HDL ea boleng bo holimo	VHDL
ModelSim – Intel FPGA Edition/ ModelSim – Intel FPGA Starter Edition	Ee	Ee
VCS/VCS MX	Ee	Ee
Riviera-PRO	Ee	Ee
Xcelium Parallel	Ee	Che

3.11. Ho Ntlafatsa Moralo oa Hao
Letlapa la 52. HDMI Design Example Ho tsamaellana le Version e fetileng ea Intel Quartus Prime Pro Edition Software

Moqapi Example Variant	Bokhoni ba ho Ntlafatsa ho Intel Quartus Prime Pro Edition 20.3
HDMI 2.0 Moralo Example (Ts'ehetso FRL = 0)	Che

Bakeng sa moetso ofe kapa ofe o sa lumellaneng exampHo phaella moo, o lokela ho etsa se latelang:

1. Hlahisa sebopeho se secha sa example ho mofuta oa hajoale oa software oa Intel Quartus Prime Pro Edition o sebelisa meralo e tšoanang ea moralo oa hau o teng.
2. Bapisa moralo kaofela example directory e nang le sebopeho sa exampe hlahisitsoe ho sebelisoa mofuta oa software oa Intel Quartus Prime Pro Edition oa pejana. Koala liphetoho tse fumanoeng.

HDCP Over HDMI 2.0/2.1 Design Example

HDCP holim'a HDMI hardware moralo example e o thusa ho lekola ts'ebetso ea sebopeho sa HDCP mme e o nolofalletsa ho sebelisa karolo ho meralo ea hau ea Intel Arria 10.
Hlokomela:
Karolo ea HDCP ha e kenyellelitsoe ho software ea Intel Quartus Prime Pro Edition. Ho fihlella sebopeho sa HDCP, ikopanye le Intel ho https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.

4.1. Ts'ireletso ea Digital Content e Phahameng ka ho Fetisisa (HDCP)
High-bandwidth Digital Content Protection (HDCP) ke mofuta oa ts'ireletso ea litokelo tsa dijithale ho theha khokahano e sireletsehileng lipakeng tsa mohloli ho ponts'o.
Intel e thehile theknoloji ea mantlha, e ngolisitsoeng ka molao ke sehlopha sa Digital Content Protection LLC. HDCP ke mokhoa oa ts'ireletso oa likopi moo molaetsa oa audio/video o kentsoeng ka mokhoa o patiloeng pakeng tsa transmitter le moamoheli, ho e sireletsa khahlanong le ho kopitsa ho seng molaong.
Likarolo tsa HDCP li latela mofuta oa HDCP Specification 1.4 le mofuta oa HDCP Specification 2.3.
Li-IP tsa HDCP 1.4 le HDCP 2.3 li etsa likhomphutha tsohle ka har'a logic ea mantlha ea hardware ntle le litekanyetso tsa lekunutu (joalo ka senotlolo sa poraefete le senotlolo sa seboka) tse fumanehang ho tsoa kantle ho IP e kentsoeng.

Lethathamo la 53. Mesebetsi ea HDCP IP

HDCP IP	Mesebetsi
HDCP 1.4 IP	• Phapanyetsano ea netefatso - Khokahano ea senotlolo sa master (Km) - Moloko oa liketsahalo tse sa reroang tsa An - Computation of session key (Ks), M0 le R0. • Netefatso ka mopheta - Khokahano le netefatso ea V le V' • Ho netefatsa botšepehi ba khokahano - Khokahano ea senotlolo sa foreimi (Ki), Mi le Ri.
e tsoela pele…

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.
*Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

ISO
9001:2015
Ngodisitsoe

HDCP IP	Mesebetsi
	• Mefuta eohle ea cipher ho kenyeletsa hdcpBlockCipher, hdcpStreamCipher, hdcpRekeyCipher, le hdcpRngCipher • Letšoao la boemo ba pele ba encryption (DVI) le matshwao a ntlafetseng a encryption status (HDMI) • Jenereitara ya nnete ya dinomoro (TRNG) - E thehiloeng ho Hardware, ts'ebetsong e felletseng ea dijithale le jenereithara ea linomoro tse sa reroang
HDCP 2.3 IP	• Senotlolo sa Master (km), Senotlolo sa Thuto (ks) le tlhahiso ea nonce (rn, riv). - E tsamaellana le tlhahiso ea nomoro ea NIST.SP800-90A e sa reroang • Netefatso le phapanyetsano ea senotlolo - Ho hlahisa linomoro tse sa reroang bakeng sa rtx le rrx tse tsamaellanang le NIST.SP800-90A tlhahiso ea linomoro e sa reroang - Netefatso ea tekeno ea setifikeiti sa moamoheli (certrx) o sebelisa senotlolo sa sechaba sa DCP (kpubdcp) - 3072 bits RSASSA-PKCS#1 v1.5 - RSAES-OAEP (PKCS#1 v2.1) encryption le decryption ea Master Key (km) - Ho tlosoa ha kd (dkey0, dkey1) ho sebelisa mokhoa oa AES-CTR - Khokahano le netefatso ea H le H' - Compution of Ekh(km) le km (pairing) • Netefatso ka mopheta - Khokahano le netefatso ea V le V' - Khokahano le netefatso ea M le M' • Ho nchafatsa tsamaiso (SRM) - Netefatso ea signature ea SRM e sebelisa kpubdcp - 3072 bits RSASSA-PKCS#1 v1.5 • Phapanyetsano ea linotlolo tsa Seboka • Ho hlahisa le ho bala Edkey(ks) le riv. • Ho tlosoa ha dkey2 ho sebelisa mokhoa oa AES-CTR • Hlahloba Sebaka - Khokahano le netefatso ea L le L' - Moloko oa bohlanya (rn) • Tsamaiso ea tsamaiso ea data - Mokhoa oa AES-CTR o ipapisitse le tlhahiso ea bohlokoa ea molatsoana • Asymmetric crypto algorithms - RSA e nang le modulus bolelele ba 1024 (kpubrx) le 3072 (kpubdcp) bits - RSA-CRT (Chinese Remainder Theorem) e nang le modulus bolelele ba likotoana tse 512 (kprivrx) le exponent ea bolelele ba 512 (kprivrx) • Ts'ebetso ea "cryptographic" ea boemo bo tlase - Li-algorithms tsa Symmetric crypto • Mokhoa oa AES-CTR o nang le bolelele ba senotlolo sa 128 bits - Hash, MGF le HMAC algorithms • SHA256 • HMAC-SHA256 • MGF1-SHA256 - Jenereithara ea linomoro tsa 'nete tse sa reroang (TRNG) • NIST.SP800-90A e lumellana • Thepa ea lisebelisoa, ts'ebetsong e felletseng ea dijithale le jenereithara ea linomoro tse sa lekanyetsoang

4.1.1. HDCP Over HDMI Design Example Architecture
Karolo ea HDCP e sireletsa data ha data e fetisoa pakeng tsa lisebelisoa tse hokahaneng ka HDMI kapa li-interfaces tse ling tse sirelelitsoeng tsa HDCP.
Sistimi e sirelelitsoeng ea HDCP e kenyelletsa mefuta e meraro ea lisebelisoa:

4. HDCP Over HDMI 2.0/2.1 Design Example
683156 | 2022.12.27
• Mehloli (TX)
• Sink (RX)
• Ba pheta-phetoang
Moqapi ona example e bonts'a sistimi ea HDCP sesebelisoa se pheta-phetoang moo e amohelang data, e hlakola, ebe e hlakola data hape, 'me qetellong e fetisetsa data hape. Li-repeaters li na le lisebelisoa le liphetho tsa HDMI ka bobeli. E tiisa li-buffers tsa FIFO ho etsa phallo e tobileng ea phallo ea video ea HDMI lipakeng tsa sink ea HDMI le mohloli. E ka 'na ea etsa ts'ebetso e itseng ea matšoao, joalo ka ho fetolela livideo ho sebopeho se phahameng ka ho fetola li-buffer tsa FIFO ka Video le Image Processing (VIP) Suite IP cores.

Setšoantšo sa 29. HDCP Over HDMI Design Example Block Diagram

Litlhaloso tse latelang mabapi le meralo ea moralo example lumellana le HDCP holim'a HDMI moralo example block diagram. Ha SUPPORT FRL = 1 kapa
TŠEHETSA TSAMAISO EA SEHLOOHO sa HDCP = 1, moqapi example hierarchy e fapane hanyane le setšoantšo sa 29 leqepheng la 95 empa mesebetsi ea HDCP e ntse e le eona.
tshoanang.

1. HDCP1x le HDCP2x ke li-IP tse fumanehang ka HDMI Intel FPGA IP parameter editor. Ha o lokisa HDMI IP ka har'a mohlophisi oa paramethara, o ka nolofalletsa le ho kenyelletsa HDCP1x kapa HDCP2x kapa IPs ka bobeli e le karolo ea tsamaiso e nyenyane. Ha li-IP tsa HDCP ka bobeli li nolofalitsoe, HDMI IP e itlhophisa ka har'a topology ea cascade moo HDCP2x le HDCP1x IPs li hokahaneng ka morao-rao.
   • HDCP egress interface ea HDMI TX e romela data e sa ngolisoang ea video ea audio.
   • Lintlha tse sa ngolisoang li tla koaheloa ke "HDCP block" e sebetsang ebe e khutlisetsoa ho HDMI TX holim'a HDCP Ingress interface bakeng sa ho fetisoa holim'a sehokelo.
   • Tsamaiso ea tsamaiso ea CPU e le molaoli ea ka sehloohong oa netefatso e tiisa hore ke e le 'ngoe feela ea HDCP TX IP e sebetsang ka nako leha e le efe mme e 'ngoe ha e sebetse.
   • Ka ho tšoanang, HDCP RX e boetse e hlakola data e amohetsoeng holim'a sehokelo ho tsoa ho HDCP TX ea kantle.
2. U hloka ho hlophisa li-IP tsa HDCP ka linotlolo tsa tlhahiso ea Digital Content Protection (DCP). Kenya linotlolo tse latelang:
   Lethathamo la 54. Linotlolo tsa Tlhahiso tse fanoeng ke DCP
   

   HDCP	TK / RX	Linotlolo
   HDCP2x	TX	16 byte: Global Constant (lc128)
   	RX	• 16 byte (ho tšoana le TX): Global Constant (lc128) • 320 byte: RSA Private Key (kprivrx) • 522 bytes: RSA Public Key Certificate (certrx)
   HDCP1x	TX	• 5 byte: TX Key Selection Vector (Aksv) • 280 bytes: TX Private Device Keys (Akeys)
   	RX	• 5 byte: RX Key Selection Vector (Bksv) • 280 bytes: RX Private Device Keys (Bkeys)

   Moqapi exampe sebelisa mehopolo ea bohlokoa e le boema-kepe bo habeli, boema-kepe ba bobeli ba RAM. Bakeng sa boholo bo bonyenyane ba senotlolo joalo ka HDCP2x TX, IP e sebelisa mohopolo oa bohlokoa o sebelisa lirekoto ka mokhoa o tloaelehileng.
   Tlhokomeliso: Intel ha e fane ka linotlolo tsa tlhahiso ea HDCP le ex design example kapa Intel FPGA IPs tlas'a maemo afe kapa afe. Ho sebelisa HDCP IPs kapa moralo example, o tlameha ho ba moamoheli oa HDCP mme o fumane linotlolo tsa tlhahiso ka kotloloho ho tsoa ho Digital Content Protection LLC (DCP).
   Ho tsamaisa moralo example, o ka hlophisa memori ea senotlolo files ka nako ea ho bokella ho kenyelletsa linotlolo tsa tlhahiso kapa ho kenya tšebetsong li-blocks tsa logic ho bala ka mokhoa o sireletsehileng linotlolo tsa tlhahiso ho tsoa sesebelisoa sa polokelo ea kantle ebe o li ngola mehopolong ea bohlokoa ka nako.

3. U ka ts'oara lits'ebetso tsa "cryptographic" tse kentsoeng ho HDCP2x IP ka maqhubu afe kapa afe ho fihla ho 200 MHz. Maqhubu a oache ena a etsa qeto ea hore na lebelo la ho
   Netefatso ea HDCP2x ea sebetsa. U ka khetha ho arolelana oache ea 100 MHz e sebelisoang bakeng sa processor ea Nios II empa nako ea netefatso e tla imena habeli ha e bapisoa le ho sebelisa oache ea 200 MHz.
4. Litekanyetso tse tlamehang ho fapanyetsanoa lipakeng tsa HDCP TX le HDCP RX li fetisetsoa ka sebopeho sa HDMI DDC (I2 C serial interface) sa HDCP-
   segokanyimmediamentsi sa sebolokigolo. HDCP RX e tlameha ho hlahisa sesebelisoa se nang le kelello beseng ea I2C bakeng sa sehokelo se seng le se seng seo e se tšehetsang. Lekhoba la I2C le kopitsoa bakeng sa boema-kepe ba HDCP le aterese ea sesebelisoa ea 0x74. E tsamaisa boema-kepe ba ngoliso ba HDCP (Avalon-MM) ea HDCP2x le HDCP1x RX IPs.
5. HDMI TX e sebelisa IC master ho bala EDID ho tloha ho RX le ho fetisetsa data ea SCDC e hlokehang bakeng sa ts'ebetso ea HDMI 2.0 ho RX. E tšoanang I2C master e tsamaisoang ke processor ea Nios II e boetse e sebelisoa ho fetisa melaetsa ea HDCP lipakeng tsa TX le RX. I2C master e kentsoe ka har'a sistimi e nyane ea CPU.
6. Motlakase oa Nios II o sebetsa e le mong'a protocol ea netefatso mme o tsamaisa lirekoto tsa taolo le maemo (Avalon-MM) tsa HDCP2x le HDCP1x TX.
   IPs. Bakhanni ba software ba kenya ts'ebetsong mochini oa mmuso oa netefatso oa protocol ho kenyelletsa netefatso ea signature ea setifikeiti, phapanyetsano ea senotlolo sa master, cheke ea sebaka, phapanyetsano ea senotlolo sa seboka, pairing, tlhahlobo ea bots'epehi ba khokahano (HDCP1x), le netefatso le ba pheta-pheta, joalo ka phatlalatso ea tlhahisoleseling ea topology le phatlalatso ea tlhahisoleseling ea taolo ea molapo. Bakhanni ba software ha ba kenye tšebetsong efe kapa efe ea mesebetsi ea cryptographic e hlokoang ke protocol ea netefatso. Sebakeng seo, HDCP IP hardware e sebelisa mesebetsi eohle ea cryptographic ho netefatsa hore ha ho na litekanyetso tsa lekunutu tse ka fihlellehang.
   7. Pontšong ea 'nete ea ho pheta-pheta moo ho phatlalatsoang tlhahisoleseding ea topology holimo ho ea holimo, mochine oa Nios II o khanna Repeater Message Port (Avalon-MM) ea HDCP2x le HDCP1x RX IPs ka bobeli. Motlakase oa Nios II o hlakola RX REPEATER hanyane ho 0 ha e bona hore ho na le sebaka se hokahaneng se tlase ho HDCPcaable kapa ha ho se na noka e hokahaneng. Ntle le khokahano e tlase, sistimi ea RX e se e le moamoheli oa ho qetela, ho fapana le ho pheta-pheta. Ka lehlakoreng le leng, processor ea Nios II e beha RX REPEATER bit ho 1 ha e lemoha hore tlase e na le HDCP e nang le bokhoni.

4.2. Phallo ea Software ea Nios II
Phallo ea software ea Nios II e kenyelletsa taolo ea netefatso ea HDCP holim'a sesebelisoa sa HDMI.
Setšoantšo sa 30. Nios II processor Flowchart

1. Software ea Nios II e qala le ho seta bocha HDMI TX PLL, TX transceiver PHY, I2C master le TI retimer ea kantle.
2. Software ea Nios II e etsa khetho ea nako le nako e bonts'a lets'oao le nepahetseng ho tsoa ho potoloho ea sekhahla sa RX ho fumana hore na qeto ea video e fetohile le hore na ho hlokahala tokiso ea TX. Software e boetse e khetha lets'oao la TX hot-plug detect ho bona hore na ketsahalo ea TX hot-plug e etsahetse.
3. Ha lets'oao le nepahetseng le amohetsoe ho tsoa ho potoloho ea sekhahla sa RX, software ea Nios II e bala SCDC le boleng ba oache ea botebo ho tloha HDMI RX mme e khutlisa sehlopha sa maqhubu a oache ho latela sekhahla se bonoeng ho fumana hore na HDMI TX PLL le transceiver PHY reconfiguration lia hlokahala. Haeba TX reconfiguration e hlokahala, software ea Nios II e laela mookameli oa I2C ho romela boleng ba SCDC ho RX e ka ntle. Ebe e laela ho hlophisa bocha HDMI TX PLL le TX transceiver
   PHY, e lateloe ke ho lekanya sesebediswa, le ho seta tatelano botjha. Haeba sekhahla se sa fetohe, ha ho tlhophiso ea TX kapa ho netefatsoa bocha ha HDCP.
4. Ha ketsahalo e chesang ea TX e etsahetse, software ea Nios II e laela mong'a I2C ho romela boleng ba SCDC ho RX ea kantle, ebe o bala EDID ho tsoa ho RX.
   le ho ntlafatsa RAM ea EDID ea kahare. Software ebe e phatlalatsa tlhahisoleseling ea EDID ho ea holimo.
5. Software ea Nios II e qala ts'ebetso ea HDCP ka ho laela mong'a I2C ho bala offset 0x50 ho tsoa ho RX e kantle ho bona hore na ho na le bokhoni ba HDCP, kapa
   ho seng joalo:
   • Haeba boleng ba HDCP2Version bo khutlisitsoeng e le 1, sebaka se tlase se ka khona ho ba le HDCP2xcaable.
   • Haeba boleng bo khutlisitsoeng ba palo eohle ea 0x50 e baloang e le 0, ho ea tlase ho na le HDCP1x-cable.
   • Haeba boleng bo khutlisitsoeng ba palo eohle ea 0x50 e baloang e le 1, ho theoha ho ka etsahala hore ebe ha e na HDCP kapa ha e sebetse.
   • Haeba karolo e ka tlaase e ne e se na HDCP-e khonang kapa e sa sebetse empa hajoale e na le bokhoni ba HDCP, software e beha karolo ea REPEATER ea motho ea pheta-phetang holimo (RX) ho ea ho 1 ho bontša hore RX e se e pheta-pheta.
   • Haeba karolo e ka tlaase e ne e le HDCP-e khonang empa hajoale e sa khonehe kapa e sa sebetse, software e beha karolo ea REPEATER ho 0 ho bontša hore RX joale ke moamoheli oa pheletso.
6. Software e qala protocol ea netefatso ea HDCP2x e kenyelletsang netefatso ea saena ea setifikeiti sa RX, phapanyetsano ea senotlolo sa master, cheke ea sebaka, phapanyetsano ea senotlolo sa seboka, ho kopanya, netefatso le ba pheta-pheta joalo ka phatlalatso ea tlhahisoleseling ea topology.
7. Ha e le boemong bo netefalitsoeng, software ea Nios II e laela mookameli oa I2C hore a hlahlobe ngoliso ea RxStatus ho tsoa ho RX e kantle, 'me haeba software e lemoha hore REAUTH_REQ bit e setiloe, e qala ho netefatsa hape ebe e tima encryption ea TX.
8. Ha metsi a tlase a ntse a pheta-pheta 'me READY bit ea registara ea RxStatus e behiloe ho 1, hangata sena se bontša hore topology e tlaase e fetohile. Kahoo, software ea Nios II e laela mong'a I2C ho bala ReceiverID_List ho tloha tlase le ho netefatsa lenane. Haeba lenane le nepahetse 'me ha ho phoso ea topology e fumanoeng, software e tsoela pele ho module ea Content Stream Management. Ho seng joalo, e qala ho netefatsa hape le ho tima encryption ea TX.
9. Software ea Nios II e lokisa boleng ba ReceiverID_List le RxInfo ebe e ngolla boema-kepe ba Avalon-MM Repeater Message ea motho ea pheta-phetoang holimo (RX). Joale RX e phatlalatsa lenane ho TX ea kantle (ho ea holimo).
10. Netefatso e felile mothating ona. Software e nolofalletsa TX encryption.
11. Software e qala protocol ea netefatso ea HDCP1x e kenyelletsang phapanyetsano ea senotlolo le netefatso le ba pheta-phetoang.
12. Software ea Nios II e etsa tlhahlobo ea botšepehi ba khokahanyo ka ho bala le ho bapisa Ri' le Ri ho tsoa ho RX e kantle (tlase) le HDCP1x TX ka ho latellana. Haeba litekanyetso
    ha li tsamaellane, sena se bontša tahlehelo ea khokahano mme software e qala netefatso le ho tima encryption ea TX.
13. Haeba karolo e ka tlaase ea metsi e pheta-pheta 'me READY bit ea Bcaps register e behiloe ho 1, hangata sena se bontša hore topology e tlaase e fetohile. Kahoo, software ea Nios II e laela mong'a I2C ho bala boleng ba lenane la KSV ho tloha tlase le ho netefatsa lenane. Haeba lenane le nepahetse 'me ha ho phoso ea topology e fumanoeng, software e lokisa lenane la KSV le boleng ba Bstatus ebe e ngolla boema-kepe ba Avalon-MM Repeater Message ea motho ea pheta-phetoang holimo (RX). Joale RX e phatlalatsa lenane ho TX ea kantle (ho ea holimo). Ho seng joalo, e qala ho netefatsa hape le ho tima encryption ea TX.

4.3. Mokhoa oa ho etsa moralo
Ho theha le ho tsamaisa HDCP holim'a sebopeho sa HDMI example e na le meq e mehlanotages.

1. Hlophisa hardware.
2. Hlahisa moralo.
3. Fetola memori ea konopo ea HDCP files ho kenyelletsa linotlolo tsa hau tsa tlhahiso ea HDCP.
   a. Boloka linotlolo tse hlakileng tsa tlhahiso ea HDCP ho FPGA (Support HDCP Key Management = 0)
   b. Boloka linotlolo tsa tlhahiso ea HDCP tse kentsoeng ka har'a memori ea flash e kantle kapa EEPROM (Support HDCP Key Management = 1)
4. Kopanya moralo.
5. View liphetho.

4.3.1. Lokisa Hardware
Ea pele stage ea pontšo ke ho theha hardware.
Ha SUPPORT FRL = 0, latela mehato ena ho theha hardware bakeng sa pontšo:

1. Hokela karete ea morali ea Bitec HDMI 2.0 FMC (ntlafatso ea 11) ho lisebelisoa tsa ntlafatso tsa Arria 10 GX boema-kepeng ba FMC.
2. Hokela lisebelisoa tsa ntlafatso tsa Arria 10 GX ho komporo ea hau u sebelisa thapo ea USB.
3. Hokela thapo ya HDMI ho tswa ho sehokedi sa HDMI RX ho karete ya moradi ya Bitec HDMI 2.0 FMC ho sesebediswa sa HDMI se dumeletsweng ke HDCP, jwalo ka karete ya graphic e nang le HDMI output.
4. Hokela thapo e 'ngoe ea HDMI ho tloha ho sehokelo sa HDMI TX ho karete ea morali ea Bitec HDMI 2.0 FMC ho sesebelisoa sa HDMI se lumelletsoeng ke HDCP, joalo ka thelevishene e nang le kenyo ea HDMI.

Ha SUPPORT FRL = 1, latela mehato ena ho theha hardware bakeng sa pontšo:

1. Hokela karete ea morali ea Bitec HDMI 2.1 FMC (Revision 9) ho lisebelisoa tsa ntlafatso tsa Arria 10 GX boema-kepeng ba FMC.
2. Hokela lisebelisoa tsa ntlafatso tsa Arria 10 GX ho komporo ea hau u sebelisa thapo ea USB.
3. Hokela lithapo tsa HDMI 2.1 Sehlopha sa 3 ho tloha ho sehokelo sa HDMI RX ho karete ea morali ea Bitec HDMI 2.1 FMC ho mohloli oa HDMI 2.1 o lumelletsoeng ke HDCP, joalo ka Quantum Data 980 48G Generator.
4. Hokela lithapo tse ling tsa HDMI 2.1 Category 3 ho tloha sehokelong sa HDMI TX ho karete ea morali ea Bitec HDMI 2.1 FMC ho sinki e lumelletsoeng ke HDCP ea HDMI 2.1, joalo ka
   Quantum Data 980 48G Analyzer.

4.3.2. Hlahisa Moralo
Ka mor'a ho theha hardware, o hloka ho hlahisa moralo.
Pele o qala, etsa bonnete ba hore o kenya sebopeho sa HDCP ho software ea Intel Quartus Prime Pro Edition.

1. Tobetsa Lisebelisoa ➤ IP Catalog, ebe u khetha Intel Arria 10 e le lelapa la sesebelisoa se shebiloeng.
   Hlokomela: Moetso oa HDCP example e ts'ehetsa feela lisebelisoa tsa Intel Arria 10 le Intel Stratix® 10.
2. Ho IP Catalog, fumana le ho penya habeli HDMI Intel FPGA IP. Ho hlaha fensetere e ncha ea ho fetola IP.
3. Hlalosa lebitso la boemo bo holimo bakeng sa IP ea hau ea tloaelo. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file bitsetsoe .qsys kapa .ip.
4. Tobetsa OK. Mohlophisi oa parameter oa hlaha.
5. Ho tab ea IP, lokisa li-parameter tse lakatsehang bakeng sa TX le RX ka bobeli.
6. Bulela Support HDCP 1.4 kapa Support HDCP 2.3 parameter ho hlahisa sebopeho sa HDCP example.
7. Bulela "Ts'ehetso ea HDCP Key Management parameter haeba u batla ho boloka senotlolo sa tlhahiso ea HDCP ka mokhoa o kentsoeng mohopolong oa flash flash kapa EEPROM. Ho seng joalo, tima "Tšehetso ea HDCP Key Management" ho boloka senotlolo sa tlhahiso ea HDCP ka mokhoa o hlakileng ho FPGA.
8. Ka Moqapi Exampho tab, khetha Arria 10 HDMI RX-TX Retransmit.
9. Khetha Synthesis ho hlahisa sebopeho sa hardware example.
10. Bakeng sa Hlahisa File Fomata, khetha Verilog kapa VHDL.
11. Bakeng sa Target Development Kit, khetha Arria 10 GX FPGA Development Kit. Haeba u khetha lisebelisoa tsa nts'etsopele, joale sesebelisoa se shebiloeng (se khethiloeng mohatong oa 4) se fetoha ho bapisa sesebelisoa ho kit ea nts'etsopele. Bakeng sa Arria 10 GX FPGA Development Kit, sesebelisoa sa kamehla ke 10AX115S2F45I1SG.
12. Tobetsa Hlahisa Example Design ho hlahisa morero files le lenaneo la lenaneo la Executable and Linking Format (ELF). file.

4.3.3. Kenyelletsa Linotlolo tsa Tlhahiso ea HDCP
4.3.3.1. Boloka linotlolo tse hlakileng tsa tlhahiso ea HDCP ho FPGA (Support HDCP Key Tsamaiso = 0)
Kamora ho etsa moralo, hlophisa memori ea senotlolo sa HDCP files ho kenyelletsa linotlolo tsa hau tsa tlhahiso.
Ho kenyelletsa linotlolo tsa tlhahiso, latela mehato ena.

1. Fumana memori ea senotlolo e latelang files ho /rtl/hdcp/ directory:
   • hdcp2x_tx_kmem.v
   • hdcp2x_rx_kmem.v
   • hdcp1x_tx_kmem.v
   • hdcp1x_rx_kmem.v
2. Bula faele ea hdcp2x_rx_kmem.v file 'me u fumane senotlolo sa feksimile se boletsoeng esale pele R1 bakeng sa Moamoheli oa Setifikeiti sa Sechaba le RX Private Key le Global Constant joalo ka ha ho bonts'itsoe ho ex.ampka tlase.
   Setšoantšo sa 31. Wire Array of Facsimile Key R1 bakeng sa Moamoheli oa Setifikeiti sa Sechaba.
   Setšoantšo sa 32. Wire Array ea Facsimile Key R1 bakeng sa RX Private Key le Global Constant
   
3. Fumana setšoantšisi bakeng sa linotlolo tsa tlhahiso 'me u nkele linotlolo tsa hau tsa tlhahiso sebakeng sa tsona sa terata ka sebopeho se seholo sa endian.
   Setšoantšo sa 33. Wire Array of HDCP Production Keys (Sebaka sa Sebaka)
   
4. Pheta Mohato oa 3 bakeng sa memori e meng eohle ea bohlokoa files. Ha o qetile ho kenyelletsa dikonopo tsa hao tsa tlhahiso memoring yohle ya dikonopo files, etsa bonnete ba hore USE_FACSIMILE parameter e behiloe ho 0 ho sebopeho sa example boemo bo holimo file (a10_hdmi2_demo.v)

4.3.3.1.1. HDCP Key Mapping ho tloha DCP Key Files
Likarolo tse latelang li hlalosa 'mapa oa linotlolo tsa tlhahiso ea HDCP tse bolokiloeng ka konopo ea DCP files ka har'a lethathamo la terata la HDCP kmem files.
4.3.3.1.2. hdcp1x_tx_kmem.v le hdcp1x_rx_kmem.v files
Bakeng sa hdcp1x_tx_kmem.v le hdcp1x_rx_kmem.v files

• Tsena tse peli files ba arolelana sebopeho se tšoanang.
• Ho tseba senotlolo se nepahetseng sa HDCP1 TX DCP file bakeng sa hdcp1x_tx_kmem.v, etsa bonnete ba hore li-byte tse 4 tsa pele tsa file ke "0x01, 0x00, 0x00, 0x00".
• Ho tseba senotlolo se nepahetseng sa HDCP1 RX DCP file bakeng sa hdcp1x_rx_kmem.v, etsa bonnete ba hore li-byte tse 4 tsa pele tsa file ke "0x02, 0x00, 0x00, 0x00".
• Linotlolo tse ho konopo ea DCP files li ka sebopeho sa li-endian tse nyane. Ho sebelisoa ho kmm files, o tlameha ho li fetolela ho li-big-endian.

Setšoantšo sa 34. 'Mapa oa Byte ho tloha senotlolo sa HDCP1 TX DCP file ho hdcp1x_tx_kmem.v

Hlokomela:
Nomoro ea byte e hlaha ka sebopeho se ka tlase:

• Boholo ba senotlolo ka li-byte * nomoro ea senotlolo + nomoro ea byte moleng oa hona joale + offset e sa khaotseng + boholo ba mela ka li-byte * nomoro ea mola.
• 308*n e bonts'a hore senotlolo se seng le se seng se na le li-byte tse 308.
• 7*y e bontša hore mola o mong le o mong o na le li-byte tse 7.

Setšoantšo sa 35. Senotlolo sa HDCP1 TX DCP file ho tlatsoa ka boleng ba litšila

Setšoantšo sa 36. Mehala ea Lithapo tsa hdcp1x_tx_kmem.v
Example ea hdcp1x_tx_kmem.v le kamoo terata ea eona e hlophisang 'mapa ho ea peleample senotlolo sa HDCP1 TX DCP file ho Setšoantšo sa 35 leqepheng la 105 .

4.3.3.1.3. hdcp2x_rx_kmem.v file
Bakeng sa hdcp2x_rx_kmem.v file

• Ho tseba senotlolo se nepahetseng sa HDCP2 RX DCP file bakeng sa hdcp2x_rx_kmem.v, etsa bonnete ba hore li-byte tse 4 tsa pele tsa file ke "0x00, 0x00, 0x00, 0x02".
• Linotlolo tse ho konopo ea DCP files li ka sebopeho sa li-endian tse nyane.

Setšoantšo sa 37. 'Mapa oa Byte ho tloha senotlolo sa HDCP2 RX DCP file ho hdcp2x_rx_kmem.v
Setšoantšo se ka tlase se bonts'a 'mapa oa byte o hlakileng ho tsoa ho konopo ea HDCP2 RX DCP file ho hdcp2x_rx_kmem.v.

Hlokomela:
Nomoro ea byte e hlaha ka sebopeho se ka tlase:

• Boholo ba senotlolo ka li-byte * nomoro ea senotlolo + nomoro ea byte moleng oa hona joale + offset e sa khaotseng + boholo ba mela ka li-byte * nomoro ea mola.
• 862*n e bonts'a hore senotlolo se seng le se seng se na le li-byte tse 862.
• 16*y e bontša hore mola o mong le o mong o na le li-byte tse 16. Ho na le mokhelo ho cert_rx_prod moo ROW 32 e nang le li-byte tse 10 feela.

Setšoantšo sa 38. Senotlolo sa HDCP2 RX DCP file ho tlatsoa ka boleng ba litšila

Setšoantšo sa 39. Lisebelisoa tsa Wire Arrays tsa hdcp2x_rx_kmem.v
Palo ena e bonts'a marang-rang a hdcp2x_rx_kmem.v (cert_rx_prod, kprivrx_qinv_prod, le lc128_prod) 'mapa ho ea pele.ample senotlolo sa HDCP2 RX DCP file in
Setšoantšo sa 38 leqepheng la 108 .

4.3.3.1.4. hdcp2x_tx_kmem.v file
Bakeng sa hdcp2x_tx_kmem.v file:

• Ho tseba senotlolo se nepahetseng sa HDCP2 TX DCP file bakeng sa hdcp2x_tx_kmem.v, etsa bonnete ba hore li-byte tse 4 tsa pele tsa file ke "0x00, 0x00, 0x00, 0x01".
• Linotlolo tse ho konopo ea DCP files li ka sebopeho sa li-endian tse nyane.
• Ntle le moo, o ka sebelisa lc128_prod ho tloha hdcp2x_rx_kmem.v ka kotloloho ho hdcp2x_tx_kmem.v. Linotlolo li arolelana litekanyetso tse tšoanang.

Setšoantšo sa 40. Mohala oa mohala oa hdcp2x_tx_kmem.v
Palo ena e bonts'a 'mapa o nepahetseng oa li-byte ho tsoa ho konopo ea HDCP2 TX DCP file ho hdcp2x_tx_kmem.v.

4.3.3.2. Boloka linotlolo tsa tlhahiso ea HDCP tse kentsoeng mohopolong oa kantle oa flash kapa EEPROM (Tsehetsa HDCP Key Management = 1)
Setšoantšo sa 41. High Level Overview ea HDCP Key Management

Ha Ts'ehetso ea Ts'ebetso ea Ts'ebetso ea Ts'ehetso ea HDCP e buletsoe, u tšoara taolo ea encryption ea senotlolo sa tlhahiso ea HDCP ka ho sebelisa sesebelisoa sa senotlolo sa encryption (KEYENC) le moralo oa bohlokoa oa mananeo oo Intel e fanang ka ona. U tlameha ho fana ka linotlolo tsa tlhahiso ea HDCP le senotlolo sa ts'ireletso sa 128 bits HDCP. Senotlolo sa tšireletso sa HDCP
e pata senotlolo sa tlhahiso ea HDCP ebe e boloka senotlolo mohopolong oa flash oa kantle (mohlalaample, EEPROM) ho karete ea morali oa HDMI.
Bulela paramethara ea Ts'ehetso ea Ts'ebetso ea HDCP 'me karolo ea bohlokoa ea ho hlakola (KEYDEC) e fumanehe ho HDCP IP cores. Tšireletso e tšoanang ea HDCP
senotlolo se lokela ho sebelisoa ho KEYDEC ho fumana linotlolo tsa tlhahiso ea HDCP ka nako ea ho sebetsa bakeng sa lienjineri tsa ho sebetsa. KEYENC le KEYDEC li tšehetsa Atmel AT24CS32 32-Kbit serial EEPROM, Atmel AT24C16A 16-Kbit serial EEPROM le lisebelisoa tse lumellanang tsa I2C EEPROM tse nang le bonyane boholo ba 16-Kbit rom.

Hlokomela:

1. Bakeng sa HDMI 2.0 FMC karete ea morali Revision 11, etsa bonnete ba hore EEPROM e kareteng ea morali ke Atmel AT24CS32. Ho na le mefuta e 'meli e fapaneng ea EEPROM e sebelisitsoeng ho Bitec HDMI 2.0 FMC karete ea morali Revision 11.
2. Haeba o ne o kile oa sebelisa KEYENC ho patala linotlolo tsa tlhahiso ea HDCP mme o bulela Ts'ehetso ea Ts'ebetso ea HDCP ka mofuta oa 21.2 kapa pejana, o hloka ho hlakisa linotlolo tsa tlhahiso ea HDCP o sebelisa sesebelisoa sa software sa KEYENC le ho nchafatsa HDCP IPs ho tsoa ho mofuta oa 21.3.
   ho ya pele.

4.3.3.2.1. Intel KEYENC
KEYENC ke sesebelisoa sa software sa taelo seo Intel e se sebelisang ho patala linotlolo tsa tlhahiso ea HDCP ka senotlolo sa ts'ireletso sa 128 bits HDCP seo u fanang ka sona. KEYENC e hlahisa linotlolo tsa tlhahiso ea HDCP tse kentsoeng ka hex kapa bin kapa hlooho file sebopeho. KEYENC e boetse e hlahisa mif file e nang le senotlolo sa tshireletso sa 128 bits HDCP. KEYDEC
e hloka mf file.

Tlhokahalo ea Sisteme:

1. mochini oa x86 64-bit o nang le Windows 10 OS
2. Sephutheloana se ka tsamaisoang hape sa Visual C++ bakeng sa Visual Studio 2019(x64)

Hlokomela:
U tlameha ho kenya Microsoft Visual C++ bakeng sa VS 2019. U ka hlahloba hore na Visual C++ e ka tsamaisoang bocha e kentsoe ho tsoa ho Windows ➤ Panel ea Taolo ➤ Mananeo le Likarolo. Haeba Microsoft Visual C++ e kentsoe, u ka bona Visual C++ xxxx
E ka abeloa bocha (x64). Ho seng joalo, o ka khoasolla le ho kenya Visual C ++
E ka tsamaisoa hape ho tsoa ho Microsoft websebaka. Sheba lintlha tse amanang le khokahanyo ea download.

Letlapa la 55. KEYENC Command Line Options

Likhetho tsa Mola oa Taelo	Khang/ Tlhaloso
-k	<HDCP protection key file> Mongolo file e nang le senotlolo sa ts'ireletso sa li-bits tse 128 feela ho hexadecimal. Example: f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff
-hdcp1tx	<HDCP 1.4 TX production keys file> Linotlolo tsa tlhahiso ea li-transmitter tsa HDCP 1.4 file ho tsoa ho DCP (.bin file)
-hdcp1rx	<HDCP 1.4 RX production keys file> Linotlolo tsa tlhahiso ea moamoheli oa HDCP 1.4 file ho tsoa ho DCP (.bin file)
-hdcp2tx	<HDCP 2.3 TX production keys file> Linotlolo tsa tlhahiso ea li-transmitter tsa HDCP 2.3 file ho tsoa ho DCP (.bin file)
-hdcp2rx	<HDCP 2.3 RX production keys file> Linotlolo tsa tlhahiso ea moamoheli oa HDCP 2.3 file ho tsoa ho DCP (.bin file)
-hdcp1txkeys	Hlalosa lethathamo la linotlolo bakeng sa tlhahiso e khethiloeng (.bin) files -hdcp1txkeys|hdcp1rxkeys|hdcp2rxkeys nm kae n = senotlolo sa ho qala (1 kapa >1) m = senotlolo sa ho qetela (n kapa > n) ExampLe: Khetha linotlolo tse 1 ho isa ho tse 1000 ho HDCP 1.4 TX ka 'ngoe, HDCP 1.4 RX le HCDP 2.3 Linotlolo tsa tlhahiso ea RX file. "-hdcp1txkeys 1-1000 -hdcp1rxkeys 1-1000 -hdcp2rxkeys 1-1000"
-hdcp1rxkeys
-hdcp2rxkeys
e tsoela pele…

Likhetho tsa Mola oa Taelo	Khang/ Tlhaloso
	Hlokomela: 1. Haeba u sa sebelise linotlolo life kapa life tsa tlhahiso ea HDCP file, u ke ke ua hloka lethathamo la linotlolo tsa HDCP. Haeba u sa sebelise khang molaong oa taelo, lenane la senotlolo sa kamehla ke 0. 2. U ka boela ua khetha index e fapaneng ea linotlolo bakeng sa linotlolo tsa tlhahiso ea HDCP file. Leha ho le joalo, palo ea linotlolo e lokela ho lumellana le likhetho tse khethiloeng. Example: Khetha linotlolo tse 100 tse fapaneng Khetha linotlolo tsa pele tsa 100 ho tsoa ho linotlolo tsa tlhahiso ea HDCP 1.4 TX file "-hdcp1txkeys 1-100" Khetha linotlolo tsa 300 ho isa ho 400 bakeng sa linotlolo tsa tlhahiso ea HDCP 1.4 RX file "-hdcp1rxkeys 300-400" Khetha linotlolo tsa 600 ho isa ho 700 bakeng sa linotlolo tsa tlhahiso ea HDCP 2.3 RX file "-hdcp2rxkeys 600-700"
-o	Sephetho file sebopeho . Kamehla ke hex file. Hlahisa linotlolo tsa tlhahiso ea HDCP tse kentsoeng ka har'a binary file sebopeho: -o bin Hlahisa linotlolo tsa tlhahiso ea HDCP tse kentsoeng ka hex file sebopeho: -o hex Hlahisa linotlolo tsa tlhahiso ea HDCP tse kentsoeng hloohong file sebopeho: -oh
– hlahloba linotlolo	Printa nomoro ea linotlolo tse fumanehang ha u kenya files. ExampLe:
	keyenc.exe -hdcp1tx file> -hdcp1rx <HDCP 1.4 RX production keys file> -hdcp2tx file> -hdcp2rx file> -hlahloba linotlolo
	Hlokomela: sebelisa parameter -check-keys qetellong ea mola oa taelo joalokaha ho boletsoe ka holimo example.
– phetolelo	Hatisa nomoro ea mofuta oa KEYENC

U ka khetha ka boikhethelo linotlolo tsa tlhahiso tsa HDCP 1.4 le/kapa HDCP 2.3 hore u li khethe. Bakeng sa mohlalaample, ho sebelisa feela linotlolo tsa tlhahiso ea HDCP 2.3 RX ho encrypt, sebelisa feela -hdcp2rx
<HDCP 2.3 RX production keys file> -hdcp2rxkeys ho li-parameter tsa mola oa taelo.
Letlapa la 56. KEYENC Tloaelehileng Molaetsa Tataiso ea Molaetsa

Molaetsa oa Phoso	Tataiso
PHOSO: Senotlolo sa tšireletso sa HDCP file e hlokang	Ha ho na paramethara ea mola oa taelo -k file>
PHOSO: senotlolo e lokela ho ba linomoro tse 32 tsa hex (mohlala, f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff)	Senotlolo sa tšireletso sa HDCP file e lokela ho ba le feela senotlolo sa tšireletso sa HDCP ka linomoro tse 32 tsa hexadecimal.
PHOSO: Ka kopo, bolela palo ea linotlolo	Lethathamo la linotlolo ha lea hlalosoa bakeng sa linotlolo tse fanoeng tsa tlhahiso ea HDCP file.
PHOSO: Lethathamo la linotlolo le fosahetse	Lintlha tsa bohlokoa tse boletsoeng bakeng sa -hdcp1txkeys kapa -hdcp1rxkeys kapa -hdcp2rxkeys ha lia nepahala.
PHOSO: ha e khone ho thehaFilelebitso>	Lekola tumello ea foldara ho keyennc.exe e ntse e sebetsa.
PHOSO: -hdcp1txkeys ha e sebetse	Mofuta oa ho kenya linotlolo tsa tlhahiso ea HDCP 1.4 TX ha o sebetse. Sebopeho se nepahetseng ke “-hdcp1txkeys nm” moo n >= 1, m >= n.
PHOSO: -hdcp1rxkeys ha e sebetse	Sebopeho sa mefuta ea lintho tse kentsoeng bakeng sa linotlolo tsa tlhahiso ea HDCP 1.4 RX ha se sebetse. Sebopeho se nepahetseng ke “-hdcp1rxkeys nm” moo n >= 1, m >= n.
PHOSO: -hdcp2rxkeys ha e sebetse	Sebopeho sa mefuta ea lintho tse kentsoeng bakeng sa linotlolo tsa tlhahiso ea HDCP 2.3 RX ha se sebetse. Sebopeho se nepahetseng ke “-hdcp2rxkeys nm” moo n >= 1, m >= n.
e tsoela pele…

Molaetsa oa Phoso	Tataiso
PHOSO: Ha e sebetse file <filelebitso>	Linotlolo tse fosahetseng tsa tlhahiso ea HDCP file.
PHOSO: file mofuta o haellang bakeng sa -o kgetho	Tekanyetso ea mola oa taelo ha e eo bakeng sa -o .
PHOSO: ha e sebetse filelebitso -filelebitso>	<filename> ha e sebetse, ka kopo sebelisa e nepahetseng filelebitso le senang litlhaku tse khethehileng.

Encrypt Key Key bakeng sa EEPROM e le 'Ngoe
Matha mola o latelang oa taelo ho tsoa ho Windows command prompt ho encrypt key e le 'ngoe ea HDCP 1.4 TX, HDCP 1.4 RX, HDCP 2.3 TX le HDCP 2.3 RX e nang le tlhahiso. file sebopeho sa hlooho file bakeng sa EEPROM e le 'ngoe:
keync.exe -k file> -hdcp1tx file> -hdcp1rx file> -hdcp2tx file> -hdcp2rx file> -hdcp1txkeys 1-1 -hdcp1rxkeys 1-1 -hdcp2rxkeys 1-1 -oh

Encrypt N Keys bakeng sa N EEPROMs
Matha mola o latelang oa taelo ho tsoa ho Windows command prompt to encrypt N linotlolo (ho qala ho key 1) ea HDCP 1.4 TX, HDCP 1.4 RX, HDCP 2.3 TX le HDCP 2.3 RX ka tlhahiso. file sebopeho sa hex file bakeng sa N EEPROMs:
keync.exe -k file> -hdcp1tx file> -hdcp1rx file> -hdcp2tx file> -hdcp2rx file> -hdcp1txkeys 1 -hdcp1rxkeys 1- -hdcp2rxkeys 1- -o hex moo N e leng> = 1 'me e lokela ho lumellana le likhetho tsohle.

Lintlha Tse Amanang
Microsoft Visual C++ bakeng sa Visual Studio 2019
E fana ka sephutheloana sa Microsoft Visual C++ x86 se ka tsamaisoang hape (vc_redist.x86.exe) bakeng sa ho khoasolla. Haeba sehokelo se fetoha, Intel e khothaletsa hore u batle "Visual C++ redistributable" ho tsoa ho enjineng ea ho batla ea Microsoft.

4.3.3.2.2. Key Programmer
Ho hlophisa linotlolo tsa tlhahiso ea HDCP tse kentsoeng ho EEPROM, latela mehato ena:

1. Kopitsa moralo oa bohlokoa oa mananeo files ho tloha tseleng e latelang ho ea bukeng ea hau ea ho sebetsa: /hdcp2x/hw_demo/key_programmer/
2. Kopitsa sehlooho sa software file (hdcp_key .h) e hlahisitsoeng ho tsoa ho sesebelisoa sa software sa KEYENC (karolo Encrypt Single Key for Single EEPROM leqepheng la 113 ) ho software/key_programmer_src/ directory le ho e reha bocha e le hdcp_key.h.
3. Matha ./runall.tcl. Script ena e etsa litaelo tse latelang:
   • Hlahisa lethathamo la IP files
   • Hlahisa mokhoa oa Moqapi oa Sethala
   • Theha morero oa Intel Quartus Prime
   • Theha software workspace le ho haha ​​software
   • Etsa pokello e felletseng
4. Khoasolla Ntho ea Software File (.sof) ho FPGA ho hlophisa linotlolo tse kentsoeng tsa tlhahiso ea HDCP ho EEPROM.

Hlahisa moralo oa Stratix 10 HDMI RX-TX Retransmit example e nang le Support HDCP 2.3 le Support HDCP 1.4 parameters e buletsoe, ebe u latela mohato o latelang ho kenyelletsa senotlolo sa tšireletso sa HDCP.

• Kopitsa mif file (hdcp_kmem.mif) e hlahisoa ho tsoa ho KEYENC software utility (karolo Encrypt Single Key bakeng sa Single EEPROM leqepheng la 113) ho ea /quartus/hdcp/ directory.

4.3.4. Kopanya Moralo
Ka mor'a hore u kenyelle linotlolo tsa hau tsa tlhahiso ea HDCP ho FPGA kapa u hlophise linotlolo tsa tlhahiso ea HDCP tse kentsoeng ho EEPROM, joale u ka khona ho hlophisa moralo.

1. Qala software ea Intel Quartus Prime Pro Edition 'me u bule /quartus/a10_hdmi2_demo.qpf.
2. Tobetsa Ho sebetsa ➤ Qala ho Kopanya.

4.3.5. View liphetho
Qetellong ea pontšo, u tla khona ho view liphetho ho sinki ea kantle ea HDCPenabled HDMI.
Ho view liphetho tsa pontšo, latela mehato ena:

1. Matlafatsa boto ea Intel FPGA.
2. Fetola directory ho /quartus/.
3. Ngola taelo e latelang ho Nios II Command Shell ho khoasolla Software Object File (.sof) ho FPGA. nios2-configure-sof output_files/ .sof
4. Matlafatsa mohloli oa kantle oa HDMI o nolofalitsoeng ke HDCP le sink (haeba ha u so etse joalo). Sink ea kantle ea HDMI e bonts'a tlhahiso ea mohloli oa hau oa kantle oa HDMI.

4.3.5.1. Likonopo tsa Push le Mesebetsi ea LED
Sebelisa likonopo tsa push le mesebetsi ea LED botong ho laola pontšo ea hau.

Letlapa la 57. Push Button le Lipontšo tsa LED (SUPPORT FRL = 0)

Tobetsa konopo / LED	Mesebetsi
cpu_resetn	Tobetsa hang ho etsa reset ea sistimi.
user_pb[0]	Tobetsa hang ho fetolela lets'oao la HPD mohloling o tloaelehileng oa HDMI.
user_pb[1]	• Tobetsa o hatelle ho laela TX core ho romela letshwao la khouto ya DVI. • E lokolle ho romela letshwao la khouto ya HDMI. • Etsa bonnete ba hore video e kenang e sebakeng sa mebala sa 8 bpc RGB.
user_pb[2]	• Tobetsa o hatelle ho laela TX core ho emisa ho romela InfoFrames ho tsoa matshwaong a sehlopha se ka thoko. • Lokolla ho tswella pele ho romela InfoFrames ho tswa matshwaong a sehlopha se ka thoko.
mosebelisi_e lebisitsoe[0]	Boemo ba senotlolo sa RX HDMI PLL. • 0: notletsoe • 1: Notletsoe
mosebelisi_e lebisitsoe[1]	Boemo ba senotlolo sa mantlha sa RX HDMI • 0: Bonyane kanale e le 'ngoe e notletsoe • 1: Likanale tse 3 kaofela li notletsoe
mosebelisi_e lebisitsoe[2]	Boemo ba RX HDCP1x IP decryption. • 0: Ha e sebetse • 1: E sebetsa
mosebelisi_e lebisitsoe[3]	Boemo ba RX HDCP2x IP decryption. • 0: Ha e sebetse • 1: E sebetsa
mosebelisi_e lebisitsoe[4]	Boemo ba senotlolo sa TX HDMI PLL. • 0: notletsoe • 1: Notletsoe
mosebelisi_e lebisitsoe[5]	Boemo ba senotlolo sa TX transceiver PLL. • 0: notletsoe • 1: Notletsoe
mosebelisi_e lebisitsoe[6]	Boemo ba encryption ba TX HDCP1x IP. • 0: Ha e sebetse • 1: E sebetsa
mosebelisi_e lebisitsoe[7]	Boemo ba encryption ba TX HDCP2x IP. • 0: Ha e sebetse • 1: E sebetsa

Letlapa la 58. Push Button le Lipontšo tsa LED (SUPPORT FRL = 1)

Tobetsa konopo / LED	Mesebetsi
cpu_resetn	Tobetsa hang ho etsa reset ea sistimi.
user_dipsw	Phetoho ea DIP e hlalositsoeng ke mosebelisi ho fetola mokhoa oa ho feta. • TIMA (boemo ba kamehla) = Phallo HDMI RX ho FPGA e fumana EDID ho tloha siling ea kantle ebe e e hlahisa mohloling o kantle oo e hokahaneng le ona. • ON = O ka laola sekgahla se phahameng sa RX sa FRL ho tswa ho terminal ya Nios II. Taelo e fetola RX EDID ka ho laola boleng ba sekhahla sa FRL. Sheba Ho tsamaisa Moralo ka Litefiso tse fapaneng tsa FRL leqepheng la 33 bakeng sa tlhaiso-leseling e batsi mabapi le ho beha litefiso tse fapaneng tsa FRL.
e tsoela pele…

Tobetsa konopo / LED	Mesebetsi
user_pb[0]	Tobetsa hang ho fetolela lets'oao la HPD mohloling o tloaelehileng oa HDMI.
user_pb[1]	Reserved.
user_pb[2]	Tobetsa hang ho bala mangolo a SCDC ho tloha sekoting se hokahaneng le TX ea karete ea morali ea Bitec HDMI 2.1 FMC. Hlokomela: Ho nolofalletsa ho bala, o tlameha ho seta DEBUG_MODE ho 1 ho software.
user_led_g[0]	Boemo ba senotlolo sa RX FRL PLL. • 0: notletsoe • 1: Notletsoe
user_led_g[1]	Boemo ba senotlolo sa video sa RX HDMI. • 0: notletsoe • 1: Notletsoe
user_led_g[2]	Boemo ba RX HDCP1x IP decryption. • 0: Ha e sebetse • 1: E sebetsa
user_led_g[3]	Boemo ba RX HDCP2x IP decryption. • 0: Ha e sebetse • 1: E sebetsa
user_led_g[4]	Boemo ba senotlolo sa TX FRL PLL. • 0: notletsoe • 1: Notletsoe
user_led_g[5]	Boemo ba senotlolo sa video sa TX HDMI. • 0 = Notlolloa • 1 = Notletsoe
user_led_g[6]	Boemo ba encryption ba TX HDCP1x IP. • 0: Ha e sebetse • 1: E sebetsa
user_led_g[7]	Boemo ba encryption ba TX HDCP2x IP. • 0: Ha e sebetse • 1: E sebetsa

4.4. Ts'ireletso ea Senotlolo sa Encryption E Kentsoeng ho Moralo oa FPGA
Meralo e mengata ea FPGA e kenya tšebetsong encryption, 'me hangata ho na le tlhoko ea ho kenya linotlolo tsa lekunutu ho FPGA bitstream. Malapeng a macha a lisebelisoa, joalo ka Intel Stratix 10 le Intel Agilex, ho na le "Secure Device Manager block" e ka fanang ka mokhoa o sireletsehileng le ho laola linotlolo tsena tsa lekunutu. Moo likarolo tsena li le sieo, u ka boloka litaba tsa FPGA bitstream, ho kenyelletsa le linotlolo life kapa life tse kentsoeng tsa lekunutu, tse nang le encryption.
Linotlolo tsa mosebelisi li lokela ho bolokoa li bolokehile ka har'a tikoloho ea moralo oa hau, 'me ka nepo li kenyelle moralong u sebelisa ts'ebetso e sireletsehileng e ikemetseng. Mehato e latelang e bontša kamoo u ka kenyang ts'ebetso e joalo ka lisebelisoa tsa Intel Quartus Prime.

1. Ntlafatsa le ho ntlafatsa HDL ho Intel Quartus Prime sebakeng se sa sireletsehang.
2. Fetisetsa moralo sebakeng se sireletsehileng 'me u kenye ts'ebetso e ikemetseng ea ho nchafatsa senotlolo sa lekunutu. Memori ea on-chip e kentse bohlokoa ba bohlokoa. Ha konopo e nchafalitsoe, ho qala memori file (.mif) e ka fetoha 'me "quartus_cdb -update_mif" e phallang e ka fetola senotlolo sa tšireletso sa HDCP ntle le ho bokella hape. Mohato ona o potlakile haholo ho sebetsa mme o boloka nako ea pele.
3. Intel Quartus Prime bitstream ebe e koala ka senotlolo sa FPGA pele e fetisetsa bitstream e patiloeng ho khutlela tikolohong e sa sireletsehang bakeng sa tlhahlobo ea ho qetela le ho tsamaisoa.

Ho khothaletsoa ho tima phihlello eohle ea debug e ka khutlisang senotlolo sa lekunutu ho tsoa ho FPGA. O ka tima bokhoni ba ho lokisa bothata ka ho feletseng ka ho tima JTAG port, kapa ka boikgethelo tima le ho botjhaview hore ha ho na likarolo tsa debug joalo ka mohlophisi oa memori ea in-system kapa Signal Tap e ka khutlisang senotlolo. Sheba AN 556: Ho sebelisa Lisebelisoa tsa Ts'ireletso ea Moralo ho Intel FPGAs bakeng sa tlhaiso-leseling e batsi mabapi le ho sebelisa likarolo tsa ts'ireletso tsa FPGA ho kenyelletsa mehato e tobileng ea ho patala FPGA bitstream le ho hlophisa likhetho tsa ts'ireletso joalo ka ho tima J.TAG phihlello.

Hlokomela:
U ka nahana ka mohato o eketsehileng oa ho hlaka kapa ho patala ka senotlolo se seng sa senotlolo sa lekunutu polokelong ea MIF.
Lintlha Tse Amanang
AN 556: Ho sebelisa Lisebelisoa tsa Ts'ireletso ea Moralo ho Intel FPGAs

4.5. Mehopolo ea Tšireletso
Ha u sebelisa sebopeho sa HDCP, ela hloko lintlha tse latelang tsa ts'ireletso.

• Ha o rala sistimi e pheta-phetoang, o tlameha ho thibela video e amoheloang ho kena TX IP maemong a latelang:
  - Haeba video e amohetsoeng e ngolisitsoe ka HDCP (ke hore, boemo ba encryption hdcp1_enabled kapa hdcp2_enabled ho tsoa ho RX IP bo tiisitsoe) mme video e fetisoang ha e na HDCP-encrypted (ke hore encryption status hdcp1_enabled kapa hdcp2_enabled ho tsoa ho TX IP ha e tiisetsoe).
  - Haeba video e amohetsoeng ke HDCP TYPE 1 (ke hore streamid_type e tsoang ho RX IP e tiisitsoe) 'me video e fetisoang ke HDCP 1.4 e patiloe (ke hore, encryption status hdcp1_enabled ho tsoa ho TX IP e tiisitsoe)
• U lokela ho boloka lekunutu le botšepehi ba linotlolo tsa hau tsa tlhahiso ea HDCP, le linotlolo life kapa life tsa mosebelisi.
• Intel e u khothaletsa ka matla ho nts'etsapele merero efe kapa efe ea Intel Quartus Prime le mohloli oa moralo files tse nang le linotlolo tsa encryption sebakeng se sireletsehileng sa compute ho sireletsa linotlolo.
• Intel e u khothaletsa ka matla hore u sebelise likarolo tsa ts'ireletso tsa moralo ho FPGAs ho sireletsa moralo, ho kenyeletsoa linotlolo life kapa life tse kentsoeng, ho tsoa ho kopi e sa lumelloeng, boenjiniere ba morao, le t.ampho kheloha.

Lintlha Tse Amanang
AN 556: Ho sebelisa Lisebelisoa tsa Ts'ireletso ea Moralo ho Intel FPGAs

4.6. Tataiso ea ho lokisa liphoso
Karolo ena e hlalosa lets'oao le sebetsang la boemo ba HDCP le likarolo tsa software tse ka sebelisoang ho lokisa liphoso. E boetse e na le lipotso tse atisang ho botsoa (FAQ) mabapi le ho tsamaisa moralo oa example.

4.6.1. Matšoao a Boemo ba HDCP
Ho na le matšoao a 'maloa a bohlokoa ho tseba boemo ba ho sebetsa ba HDCP IP cores. Lipontšo tsena li fumaneha ho ex designample boemo bo holimo 'me li hokahantsoe le li-LED tse holim'a board:

Lebitso la Letshwao	Mosebetsi
hdcp1_enabled_rx	Boemo ba RX HDCP1x IP Decryption 0: Ha e sebetse 1: E sebetsa
hdcp2_enabled_rx	Boemo ba RX HDCP2x IP Decryption 0: Ha e sebetse 1: E sebetsa
hdcp1_enabled_tx	TX HDCP1x IP Encryption Boemo 0: Ha e sebetse 1: E sebetsa
hdcp2_enabled_tx	TX HDCP2x IP Encryption Boemo 0: Ha e sebetse 1: E sebetsa

Sheba Lethathamo la 57 leqepheng la 115 le Lethathamo la 58 leqepheng la 115 bakeng sa ho beoa ha bona ha LED.
Boemo bo sebetsang ba matšoao ana bo bontša hore HDCP IP e netefalitsoe ebile e amohela / e romela molaetsa oa video o patiloeng. Bakeng sa tsela e 'ngoe le e 'ngoe, ke HDCP1x kapa HDCP2x feela
matshwao a boemo ba encryption/decryption a sebetsa. Bakeng sa mohlalaample, haeba hdcp1_enabled_rx kapa hdcp2_enabled_rx e ntse e sebetsa, HDCP e lehlakoreng la RX e tla nolofalloa le ho hlakola video e patiloeng ho tsoa mohloling oa video o kantle.

4.6.2. Ho fetola HDCP Software Parameters
Ho nolofatsa ts'ebetso ea ho lokisa HDCP, o ka fetola maemo ho hdcp.c.
Tafole e ka tlase e akaretsa lenane la li-parameter tse ka hlophisoang le mesebetsi ea tsona.

Paramethara	Mosebetsi
SUPPORT_HDCP1X	Numella HDCP 1.4 ka lehlakoreng la TX
SUPPORT_HDCP2X	Numella HDCP 2.3 ka lehlakoreng la TX
DEBUG_MODE_HDCP	Numella melaetsa ea ho lokisa bothata bakeng sa TX HDCP
REPEATER_MODE	Lumella mokhoa oa ho pheta-pheta bakeng sa moralo oa HDCP example

Ho fetola li-parameter, fetola litekanyetso ho ea ho tse lakatsehang ho hdcp.c. Pele o qala pokello, etsa phetoho e latelang ho build_sw_hdcp.sh:

1. Fumana mola o latelang 'me u fane ka maikutlo ka oona ho thibela software e fetotsoeng file ho nkeloa sebaka ke sa pele files ho tsoa tseleng ea ho kenya Intel Quartus Prime Software.
   
2.  Matha "./build_sw_hdcp.sh" ho bokella software e ntlafalitsoeng.
3. The generated .elf file e ka kenyelletsoa moralong ka mekhoa e 'meli:
   a. Matha "nios2-jarolla -g file lebitso>". Seta sistimi ka mor'a hore ts'ebetso ea ho jarolla e phetheloe ho netefatsa ts'ebetso e nepahetseng.
   b. Matha "quartus_cdb --update_mif" ho nchafatsa qalo ea memori files. Matha assembler ho hlahisa .sof e ncha file e kenyeletsang software e ntlafalitsoeng.

4.6.3. Lipotso Tse Botsoang Khafetsa (FAQ)
Lethathamo la 59. Matšoao a ho Hloka le Litaelo

Nomoro	Ho hloleha Letshwao	Tataiso
1.	RX e amohela video e patiloeng, empa TX e romella video e tsitsitseng ka 'mala o moputsoa kapa o motšo.	Sena se bakoa ke netefatso ea TX e sa atleheng ka sinki ea kantle. Motho ea pheta-phetoang ea nang le HDCP ha aa lokela ho fetisa video ka mokhoa o sa ngolisoang haeba video e kenang e tsoang holimo e ngotsoe ka mokhoa o sireletsehileng. Ho finyella sena, video e tsitsitseng ea 'mala o moputsoa kapa o motšo e nkela video e hlahang sebaka ha letšoao la boemo ba TX HDCP la encryption le sa sebetse ha lets'oao la boemo ba RX HDCP le ntse le sebetsa. Bakeng sa litataiso tse hlakileng, sheba ho Mehopolo ea Tšireletso leqepheng la 117. Leha ho le joalo, boitšoaro bona bo ka sitisa mokhoa oa ho lokisa liphoso ha o nolofalletsa moralo oa HDCP. Ka tlase ke mokhoa oa ho tima video e thibelang moetsong oa exampLe: 1. Fumana khokahanyo e latelang ea boema-kepe boemong bo kaholimo ba sebopeho sa example. Kou ena ke ea hdmi_tx_top module. 2. Fetola khokahanyo ea boema-kepe moleng o latelang:
2.	Letšoao la boemo ba encryption ba TX HDCP lea sebetsa empa setšoantšo sa lehloa se bonts'oa siling e tlase.	Sena se bakoa ke hore sink e tlase ha e hlakole video e kentsoeng ka mokhoa o nepahetseng. Etsa bonnete ba hore o fana ka global constant (LC128) ho TX HDCP IP. Boleng bo tlameha ho ba boleng ba tlhahiso mme bo nepahale.
3.	Letšoao la boemo ba encryption ba TX HDCP ha le tsitsa kapa le lula le sa sebetse.	Sena se bakoa ke netefatso ea TX e sa atleheng ka sink e tlase. Ho bebofatsa tshebetso debugging, o ka etsa hore ho DEBUG_MODE_HDCP parameter ho hdcp.c. Sheba Ho fetola HDCP Software Parameters leqepheng la 118 mabapi le tataiso. 3a-3c e latelang e ka ba lisosa tse ka bang teng tsa ho se atlehe ha netefatso ea TX.
3a.	Software debug log e lula e hatisa molaetsa ona "HDCP 1.4 ha e tšehetsoe ke the downstream (Rx)".	Molaetsa o bontša hore sinki e tlase ha e tšehetse HDCP 2.3 le HDCP 1.4 ka bobeli. Etsa bonnete ba hore sinki e tlase e tšehetsa HDCP 2.3 kapa HDCP 1.4.
3b.	TX netefatso e hloleha halofo.	Sena se bakoa ke karolo efe kapa efe ea netefatso ea TX joalo ka netefatso ea signature, tlhahlobo ea sebaka joalo-joalo e ka hloleha. Etsa bonnete ba hore sink e tlase e sebelisa senotlolo sa tlhahiso empa eseng senotlolo sa facsimile.
3c.	Software debug log e lula e hatisa "Re-authentication	Molaetsa ona o bontša hore sink e tlase e kopile ho netefatsoa hape hobane video e amohetsoeng ha ea hlakoloa hantle. Etsa bonnete ba hore o fana ka global constant (LC128) ho TX HDCP IP. Boleng bo tlameha ho ba boleng ba tlhahiso mme boleng bo nepahetse.
e tsoela pele…

Nomoro	Ho hloleha Letshwao	Tataiso
	ea hlokahala” kamora hore netefatso ea HDCP e phetheloe.
4.	Letšoao la boemo ba RX HDCP ha le sebetse le hoja mohloli o ka holimo o nolofalitse HDCP.	Sena se bontša hore RX HDCP IP ha e e-s'o fihlele boemo bo tiisitsoeng. Ka ho sa feleng, the REPEATER_MODE paramethara e nolofalitsoe ho moralo oa mohlalaample. Haeba e REPEATER_MODE e nolofalitsoe, etsa bonnete ba hore TX HDCP IP e netefalitsoe. Ha the REPEATER_MODE parameter e nolofalitsoe, RX HDCP IP e leka ho netefatsa e le e pheta-pheta haeba TX e hokahane le sink e nang le bokhoni ba HDCP. Netefatso e emisa bohareng ha e ntse e emetse TX HDCP IP ho phethela netefatso ka sink e tlase ebe e fetisetsa RECEIVERID_LIST ho RX HDCP IP. Nako ea nako joalo ka ha e hlalositsoe ho Specification ea HDCP ke metsotsoana e 2. Haeba TX HDCP IP e sa khone ho phethela netefatso nakong ena, mohloli o ka holimo o nka netefatso e le e hlolehileng mme o qala netefatso hape joalo ka ha ho boletsoe ho Tlhaloso ea HDCP.
		Hlokomela: • Sheba Ho fetola HDCP Software Parameters leqepheng la 118 bakeng sa mokhoa oa ho tima REPEATER_MODE paramethara molemong oa ho lokisa liphoso. Ka mor'a ho thibela ho REPEATER_MODE parameter, RX HDCP IP e lula e leka ho netefatsa e le moamoheli oa pheletso. TX HDCP IP ha e kenye ts'ebetso ea netefatso.
		• Haeba the REPEATER_MODE parameter ha e sebetse, etsa bonnete ba hore senotlolo sa HDCP se fanoeng ho HDCP IP ke boleng ba tlhahiso 'me boleng bo nepahetse.
5.	Letšoao la boemo ba RX HDCP ha le tsitsa.	Sena se bolela hore RX HDCP IP e kopile ho netefatsoa hape hang ka mor'a hore naha e netefalitsoeng e fihlelle. Mohlomong sena se bakoa ke hore video e kenang e patiloeng ha ea hlakoloa ka nepo ke RX HDCP IP. Etsa bonnete ba hore kamehla lefats'e (LC128) e fanoeng ho RX HDCP IP core ke boleng ba tlhahiso 'me boleng bo nepahetse.

HDMI Intel Arria 10 FPGA IP Design Example User Guide Archives

Bakeng sa liphetolelo tsa morao-rao le tse fetileng tsa tataiso ena ea basebelisi, sheba HDMI Intel® Arria 10 FPGA IP Design Ex.ample Bukana ea Mosebelisi. Haeba IP kapa mofuta oa software o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa IP e fetileng kapa mofuta oa software.
Liphetolelo tsa IP li tšoana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihla ho v19.1. Ho tsoa ho Intel Quartus Prime Design Suite software version 19.2 kapa hamorao, IP
li-cores li na le leano le lecha la phetolelo ea IP.

Nalane ea Phetoho ea HDMI Intel Arria 10 FPGA IP Design Example Bukana ea Mosebelisi

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
2022.12.27	22.4	19.7.1	E kentse paramente e ncha ea ho khetha ntlafatso ea karete ea morali oa HDMI ho karolo ea Litlhoko tsa Hardware le Software ea moralo oa khale.ample bakeng sa HDMI 2.0 (mokhoa o seng oa FRL).
2022.07.29	22.2	19.7.0	• Tsebiso ea ho tlosoa ha karolo ea Cygwin phetolelong ea Windows* ea Nios II EDS le tlhokahalo ea ho kenya WSL bakeng sa basebelisi ba Windows*. • Karete ea morali e ntlafalitse ho tloha ho Revision 4 ho isa ho 9 moo ho hlokahalang tokomaneng eohle.
2021.11.12	21.3	19.6.1	• E ntlafalitse karoloana ea Lebenkele e kentsoeng linotlolo tsa tlhahiso ea HDCP mohopolong oa flash oa kantle kapa EEPROM (Support HDCP Key Management = 1) ho hlalosa ts'ebeliso e ncha ea software ea encryption (KEYENC). • E tlositse lipalo tse latelang: - Lethathamo la lintlha tsa Facsimile Key R1 bakeng sa RX Private Key - Lethathamo la lintlha tsa Linotlolo tsa Tlhahiso ea HDCP (Sebaka sa Sebaka) - Lethathamo la lintlha tsa senotlolo sa ts'ireletso sa HDCP (senotlolo se boletsoeng esale pele) - Senotlolo sa tšireletso sa HDCP se qalile ho hdcp2x_tx_kmem.mif - Senotlolo sa tšireletso sa HDCP se qalile ho hdcp1x_rx_kmem.mif - Senotlolo sa tšireletso sa HDCP se qalile ho hdcp1x_tx_kmem.mif • Karolwana e tlositsweng ya HDCP Key Mapping ho tswa ho DCP Key Files ho tloha Litaelong tsa Debug ho boloka linotlolo tse hlakileng tsa tlhahiso ea HDCP ho FPGA (Support HDCP Key Management = 0).
2021.09.15	21.1	19.6.0	Ho tlositsoe tšupiso ea ncsim
2021.05.12	21.1	19.6.0	• E Ekelitsoe Ha SUPPORT FRL = 1 kapa SUPPORT HDCP KEY MANAGEMENT = 1 ho tlhaloso ea Setšoantšo sa 29 HDCP Over HDMI Design Example Block Diagram. • E kentse mehato memoring ya konopo ya HDCP files in Design Walkthrough. • E kentsoe Ha U TŠEHETSA FRL = 0 karolong ea Seta thepa ea thepa. • E kentse mohato oa ho bulela parameter ea Ts'ehetso ea HDCP Key Management ho Hlahisa Moralo. • E kentse karoloana e ncha ea Lebenkele e kentsoeng linotlolo tsa tlhahiso ea HDCP mohopolong oa flash oa kantle kapa EEPROM (Support HDCP Key Management = 1).
e tsoela pele…

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
			• Ho Fetola Konopo ea Tafole ea Push le Lipontšo tsa LED ho Push Button le Lipontšo tsa LED (SUPPORT FRL = 0). • Konopo e Ekelitsoeng ea Tafole ea Push le Lipontšo tsa LED (SUPPORT FRL = 1). • E kentse khaolo e ncha Tšireletso ea Senotlolo sa Encryption E Kentsoeng Moetsong oa FPGA. • E kentse khaolo e ncha Tataiso ea Tataiso le likaroloana tsa HDCP Status Signals, Modifying HDCP Software Parameter le Lipotso Tse Atisang ho Botsoa.
2021.04.01	21.1	19.6.0	• Likarolo tse Nchafalitsoeng tsa Lipalo tse Hlokehang Bakeng sa RX-Feela kapa TX-Feela Moralo. • Lethathamo le Hlahisitsoeng ka RTL e Nchafalitsoeng Files. • Setšoantšo se ntlafalitsoeng HDMI RX Top Components. • Tlosa Karolo ea HDMI RX Top Link Training Process. • Ntlafalitse mehato ea ho Mathisa Moralo ka Litefiso tse Fapaneng tsa FRL. • Setšoantšo se ntlafalitsoeng HDMI 2.1 Design Example Clock Scheme. • Lipontšo tsa Sekema sa ho Tlisa Tafole e ntlafalitsoeng. • Setšoantšo se ntlafalitsoeng sa HDMI RX-TX Block Diagram ho eketsa kgokelo ho tloha Transceiver Arbiter ho isa TX top.
2020.09.28	20.3	19.5.0	• E tlositse molaetsa oa hore HDMI 2.1 design example ka mokhoa oa FRL e ts'ehetsa feela lisebelisoa tsa lebelo -1 ho HDMI Intel FPGA IP Design Example Tataiso ea ho Qala ka Potlako bakeng sa Lisebelisoa tsa Intel Arria 10 le HDMI 2.1 Design Example (Ts'ehetso FRL = 1) likarolo. Moralo o tšehetsa limaraka tsohle tsa lebelo. • E tlositse ls_clk lintlha tsohle tsa HDMI 2.1 design example likarolo tse amanang. Sebaka sa ls_clk ha se sa sebelisoa ho sebopeho sa example. • E ntlafalitse li-block diagrams tsa HDMI 2.1 design example ka mokhoa oa FRL ho HDMI 2.1 Design Example (Ts'ehetso ea FRL = 1), Ho theha RX- Feela kapa TX-Feela Meaho ea Likarolo tsa Moqapi, le likarolo tsa Clock Scheme. • E ntlafalitse li-directory le ho etsoa files lenaneng likarolong tsa Sebopeho sa Directory. • E tlositse matshwao a sa sebetseng, mme ya eketsa kapa ya hlophisa tlhaloso ya HDMI 2.1 design example matšoao karolong ea Interface Signals: — sys_init — txpll_frl_locked — tx_os - matšoao a txphy_rcfg* — tx_reconfig_done — txcore_tbcr — pio_in0_external_connection_export • E kentse liparamente tse latelang karolong ea Design RTL Parameters: — EDID_RAM_ADDR_WIDTH — BITEC_DAUGHTER_CARD_REV - SEBELISA FPLL - POLARITY_INVERSION
e tsoela pele…

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
			• E ntlafalitse li-block diagrams tsa HDMI 2.0 design example bakeng sa software ea Intel Quartus Prime Pro Edition ho HDMI 2.0 Design Example (Ts'ehetso ea FRL = 0), Ho theha RX-Feela kapa TX-Feela Likarolo tsa Meetso ea Meetso, le likarolo tsa Clock Scheme. • E ntlafalitse oache le ho seta bocha mabitso a lets'oao ho Dynamic Range le Mastering (HDR) karolo ea InfoFrame Insertion and Filtering. • E tlositse matshwao a sa sebetseng, mme ya eketsa kapa ya hlophisa tlhaloso ya HDMI 2.0 design example matšoao karolong ea Interface Signals: — clk_fpga_b3_p - REFCLK_FMCB_P — fmcb_la_tx_p_11 — fmcb_la_rx_n_9e — fr_click — reset_xcvr_powerup — matshwao a nios_tx_i2c* — hdmi_ti_i2c* matšoao — tx_i2c_avalon* matšoao — clock_bridge_0_in_clk_clk — reset_bridge_0_reset_reset_n — matšoao a i2c_master* — matshwao a nios_tx_i2c* — measure_valid_pio_external_connectio n_export — oc_i2c_av_slave_translator_avalon_an ti_slave_0* matshwao — powerup_cal_done_export — rx_pma_cal_busy_export — rx_pma_ch_export — rx_pma_rcfg_mgmt* matšoao • E kentse molaetsa oa hore simulation testbench ha e tšehetsoe bakeng sa meralo le Kenyelletsa I2C parameter e nolofalelitse le ho ntlafatsa molaetsa oa ketsiso karolong ea Simulation Testbench. • E ntlafalitse karolo ea Ho Ntlafatsa Moralo oa Hao.
2020.04.13	20.1	19.4.0	• E kentse molaetsa oa hore HDMI 2.1 design example ka mokhoa oa FRL e ts'ehetsa feela lisebelisoa tsa lebelo -1 ho HDMI Intel FPGA IP Design Example Tataiso ea ho Qala ka Potlako bakeng sa Lisebelisoa tsa Intel Arria 10 le Tlhaloso e Felletseng bakeng sa HDMI 2.1 Design Example (Ts'ehetso FRL = 1) likarolo. • E tsamaisitse HDCP Over HDMI Design Example bakeng sa karolo ea Intel Arria 10 Devices ho tloha ho HDMI Intel FPGA IP User Guide. • Edita Karolo ea Ho etsisa Moralo ho kenyelletsa mamelwang sampjenereithara, jenereithara ea data ea sideband, le jenereithara e thusang ea data le ho nchafatsa molaetsa o atlehileng oa papiso. • Tlosa noto e boletsoeng ketsiso e fumaneha feela bakeng sa Tšehetsa FRL meralo e nang le bokooa note. Ketsiso e se e fumaneha bakeng sa Tšehetsa FRL meralo e nolofalitsoeng hape. • E ntlafalitse tlhaloso ea likarolo ho Tlhaloso e Felletseng bakeng sa HDMI 2.1 Design Example (Ts'ehetso ea FRL E nolofalitsoe) karolo.
e tsoela pele…

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
			• E hlophisitse setšoantšo sa block ho HDMI 2.1 RX-TX Design Block Diagram, Design Components, le Ho theha likarolo tsa RX-Feela kapa TX-Only Designs bakeng sa HDMI 2.1 design example. E kentse likarolo tse ncha le likarolo tse tlositsoeng tse seng li sa sebetse. • E hlophisitse taelo ea main.c script karolong ea Ho Etsa RX-Feela kapa Meetso ea TX-Feela. • E ntlafalitse likarolo tsa Sebopeho sa Directory ho eketsa lifoldara tse ncha le files bakeng sa HDMI 2.0 le HDMI ka bobeli 2.1 moralo mohlalaamples. • E ntlafalitse karolo ea Litlhoko tsa Hardware le Software bakeng sa HDMI 2.1 design example. • E ntlafalitse block diagram le litlhaloso tsa matšoao ho Dynamic Range le Mastering (HDR) karolo ea InfoFrame InfoFrame le Filtering bakeng sa HDMI 2.1 design ex.ample. • E kentse karolo e ncha, Ho Mathisa Moralo ka Litefiso tse fapaneng tsa FRL, bakeng sa HDMI 2.1 design examples. • E ntlafalitse block diagram le litlhaloso tsa matšoao karolong ea Clock Scheme bakeng sa HDMI 2.1 design ex.ample. • Tlhaloso e ekeditsweng mabapi le switjha ya DIP ya mosebedisi karolong ya Hardware Setup bakeng sa HDMI 2.1 design example. • E ntlafalitse karolo ea Meeli ea Moralo bakeng sa HDMI 2.1 design example. • E ntlafalitse karolo ea Ho Ntlafatsa Moralo oa Hao. • E ntlafalitse likarolo tsa Simulation Testbench bakeng sa bobeli HDMI 2.0 le HDMI 2.1 design examples.
2020.01.16	19.4	19.3.0	• E ntlafalitse HDMI Intel FPGA IP Design Example Tataiso ea ho Qala e Potlakileng bakeng sa karolo ea Intel Arria 10 Devices e nang le tlhahisoleseling mabapi le sebopeho se sa tsoa eketsoa sa HDMI 2.1.ample ka mokhoa oa FRL. • E kentse khaolo e ncha, Tlhaloso e qaqileng bakeng sa HDMI 2.1 Design Example (Ts'ehetso ea FRL E nolofalitsoe) e nang le lintlha tsohle tse amanang le moralo o mocha oa example. • E reha bocha HDMI Intel FPGA IP Design Example Tlhaloso e Felletseng ho Tlhaloso e Felletseng bakeng sa HDMI 2.0 Design Example bakeng sa ho hlaka ho molemo.
2019.10.31	18.1	18.1	• E kentsoe e hlahisitsoeng files sephuthelong sa tx_control_src: ti_i2c.c le ti_i2c.h. • Tšehetso e ekelitsoeng bakeng sa ntlafatso ea karete ea morali oa FMC ea 11 ho Hardware le Litlhoko tsa Software le ho Kopanya le ho Lekola likarolo tsa Moralo. • E tlositse karolo ea Moeli oa Moetso. Moeli mabapi le tlolo ea nako ho litšitiso tse phahameng tsa skew o ile oa rarolloa ka mofuta 18.1 ea HDMI Intel FPGA IP. • E kentse paramethara e ncha ea RTL, BITEC_DAUGHTER_CARD_REV, ho u nolofalletsa ho khetha ntlafatso ea karete ea morali ea Bitec HDMI.
e tsoela pele…

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
			• E ntlafalitse tlhaloso ea matshwao a fmcb_dp_m2c_p le fmcb_dp_c2m_p ho kenyelletsa lintlha tse mabapi le lintlafatso tsa likarete tsa morali tsa FMC 11, 6, le 4. • E kentse matšoao a macha a latelang bakeng sa ntlafatso ea karete ea morali oa Bitec 11: — hdmi_tx_ti_i2c_sda — hdmi_tx_ti_i2c_scl — oc_i2c_master_ti_avalon_anti_slave_a aterese — oc_i2c_master_ti_avalon_anti_slave_w rite — oc_i2c_master_ti_avalon_anti_slave_r eaddata — oc_i2c_master_ti_avalon_anti_slave_w ritedata — oc_i2c_master_ti_avalon_anti_slave_w aitrequest • E kentse karolo e mabapi le Ho Ntlafatsa Moralo oa Hao.
2017.11.06	17.1	17.1	• E rehetsoe bocha HDMI IP core ho HDMI Intel FPGA IP joalo ka Intel rebranding. • Fetola lentsoe Qsys ho ba Moqapi oa Platform. • Tlhahisoleseding e ekeditsweng mabapi le Dynamic Range le Mastering InfoFrame (HDR) ho kenya le tshebetso ya ho sefa. • E ntlafalitse sebopeho sa bukana: - E kentse lifoldara tsa script le software le files. - E ntlafalitsoe tse tloaelehileng le HDr files. - E tlositsoe atx files. - E fapane files ea Intel Quartus Prime Standard Edition le Intel Quartus Prime Pro Edition. • E ntlafalitse karolo ea Ho Hlahisa Moralo ho kenya sesebelisoa se sebelisoang e le 10AX115S2F4I1SG. • E fetotse sekhahla sa data sa transceiver bakeng sa 50-100 MHz TMDS frequency frequency to 2550-5000 Mbps. • E ntlafalitse lintlha tsa lihokelo tsa RX-TX tseo o ka lokollang konopo ea user_pb[2] ho tima ho sefa kantle. • E ntlafalitse setšoantšo sa phallo ea software ea Nios II e kenyelletsang litaolo tsa I2C master le HDMI mohloli. • Boitsebiso bo ekelitsoeng mabapi le Moqapi Example GUI parameters. • E kentse HDMI RX le TX Top meralo ea moralo. • E kentse matshwao ana a HDMI RX le TX a boemo bo hodimo: — mgmt_clk - seta bocha — i2c_clk — hdmi_clk_in - E tlositse matšoao ana a HDMI RX le TX a boemo bo holimo: • mofuta • i2c_clk
e tsoela pele…

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
			• E kentse molaetsa oa hore setlama sa analoge ea transceiver e lekoa bakeng sa karete ea Morali ea Intel Arria 10 FPGA le Bitec HDMI 2.0 Daughter. U ka fetola sebopeho sa analog bakeng sa boto ea hau. • E kentse sehokelo bakeng sa ho sebetsa ho qoba jitter ea PLL cascading kapa litselana tsa lioache tse sa inehelang bakeng sa oache ea referense ea Intel Arria 10 PLL. • E kentse molaetsa oa hore u ke ke ua sebelisa transceiver RX pin e le CDR refclk bakeng sa HDMI RX kapa e le TX PLL refclk bakeng sa HDMI TX. • E kentse molaetsa mabapi le mokhoa oa ho kenya set_max_skew constraint bakeng sa meralo e sebelisang TX PMA le PCS bonding.
2017.05.08	17.0	17.0	• E rehiloe bocha joalo ka Intel. • Nomoro ea karolo e fetotsoeng. • E ntlafalitse sebopeho sa bukana: - HDr e ekelitsoeng files. - E fetotsoe qsys_vip_passthrough.qsys ho nios.qsys. - E ekelitsoe filee etselitsoe Intel Quartus Prime Pro Edition. • Tlhahisoleseding e ntlafalitsoeng ea hore RX-TX Link block e boetse e etsa sefa ka ntle ho High Dynamic Range (HDR) Infoframe ho tloha ho HDMI RX data e thusang le ho kenya ex.ample HDR Infoframe ho data e thusang ea HDMI TX ka Avalon ST multiplexer. • E kentse molaetsa bakeng sa tlhaloso ea Transceiver Native PHY hore ho kopana le tlhokahalo ea HDMI TX inter-channel skew, o hloka ho seta khetho ea mokhoa oa TX bonding ho Arria 10 Transceiver Native PHY parameter editor ho PMA le PCS tlamahano. • Tlhaloso e ntlafalitsoeng bakeng sa matshwao a os le metha. • Fetotse oversampling factor bakeng sa sekhahla sa data sa transceiver se fapaneng sebakeng se seng le se seng sa maqhubu a oache ea TMDS ho ts'ehetsa sekema sa oache e tobileng ea TX FPLL. • Fetotse sekeme sa TX IOPLL ho TX FPLL cascade clocking scheme ho TX FPLL direct scheme. • E kentse matshwao a tlhophiso botjha ya TX PMA. • E fetotse li-overs tsa USER_LED[7]ampboemo ba ling. 1 e bontša ho fetaampled (tekanyo ya data <1,000 Mbps ho sesebelisoa sa Arria 10). • Moetso o ntlafalitsoeng oa HDMI Example Tafole e tšehelitsoeng ea Simulators. VHDL ha e tšehetsoe bakeng sa NCSim. • Sehokelo se kentsoeng ho mofuta o bolokoang oa Arria 10 HDMI IP Core Design Example Bukana ea Mosebelisi.
2016.10.31	16.1	16.1	Tokollo ea pele.

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

Online Version
Romella Maikutlo
ID: 683156
Phetolelo: 2022.12.27

Litokomane / Lisebelisoa

Intel HDMI Arria 10 FPGA IP Design Example [pdf] Bukana ea Mosebelisi HDMI Arria 10 FPGA IP Design Example, HDMI Arria, 10 FPGA IP Design Example, Moqapi Example

Litšupiso

• Bukana ea Mosebelisi