GPIO Intel® FPGA IP User Guide

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Intel® Arria® 10 le Intel® Cyclone® 10 GX Devices

E ntlafalitsoe bakeng sa Intel® Quartus® Prime Design Suite: 21.2
Mofuta oa IP: 20.0.0

Online Version                                                               ID: 683136
Romella Maikutlo             ug-altera_gpio            Mofuta: 2021.07.15

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GPIO Intel® FPGA IP ea mantlha e tšehetsa likarolo le likarolo tsa morero oa kakaretso oa I/O (GPIO). U ka sebelisa li-GPIO lits'ebetsong tse akaretsang tse sa tobang ho li-transceivers, li-memory interface, kapa LVDS.

The GPIO IP core e fumaneha bakeng sa lisebelisoa tsa Intel Arria® 10 le Intel Cyclone® 10 GX feela. Haeba u falla ho tsoa ho lisebelisoa tsa Stratix® V, Arria V, kapa Cyclone V, u tlameha ho falla ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, kapa ALTIOBUF IP cores.

Lintlha Tse Amanang

• Phallo ea Phallo ea IP bakeng sa Arria V, Cyclone V, le Stratix V Devices leqepheng la 22
• Litaelo tsa Ts'ebetsong tsa Intel Stratix 10 I/O
  E fana ka tataiso ea mantlha ea GPIOIP bakeng sa lisebelisoa tsa Intel Stratix 10.
• Kenyelletso ea Intel FPGA IP Cores
  E fana ka tlhaiso-leseling e akaretsang mabapi le li-cores tsohle tsa Intel FPGA IP, ho kenyelletsa le parameterizing, ho hlahisa, ho ntlafatsa, le ho etsisa li-cores tsa IP.
• Ho theha Phetolelo e Ikemetseng ea IP le Qsys Simulation Scripts
  Etsa mongolo oa papiso o sa hlokeng lintlafatso tsa software kapa lintlafatso tsa mofuta oa IP.
• Mekhoa e Metle ea Tsamaiso ea Morero
  Litaelo tsa taolo e nepahetseng le ho nkeha habonolo ha projeke ea hau le IP files.
• GPIO Intel FPGA IP User Guide Archives leqepheng la 24
  E fana ka lethathamo la litataiso tsa basebelisi bakeng sa liphetolelo tse fetileng tsa GPIO IP core.
• Habeli Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, le ALTDDIO_BIDIR) IP Cores User Guide
• I/O Buffer (ALTIOBUF) IP Core User Guide

Tlhahisoleseding ea Phatlalatso bakeng sa GPIO Intel FPGA IP

Liphetolelo tsa Intel FPGA IP li tsamaisana le mefuta ea software ea Intel Quartus® Prime Design Suite ho fihlela v19.1. Ho qala ka Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP e na le leano le lecha la phetolelo.

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Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

ISO 9001:2015 E Ngolisitsoe

Nomoro ea Intel FPGA IP (XYZ) e ka fetoha ka mofuta o mong le o mong oa software ea Intel Quartus Prime. Phetoho ho:

• X e bontša phetoho e kholo ea IP. Haeba u nchafatsa software ea Intel Quartus Prime, u tlameha ho nchafatsa IP.
• Y e bonts'a IP e kenyelletsa likarolo tse ncha. Nchafatsa IP ea hau ho kenyelletsa likarolo tsena tse ncha.
• Z e bonts'a IP e kenyelletsa liphetoho tse nyane. Hlahisa IP ea hau bocha ho kenyelletsa liphetoho tsena.

Letlapa la 1. GPIO Intel FPGA IP Core ea Hona joale Boitsebiso ba Phallo

Ntho	Tlhaloso
IP Version	20.0.0
Intel Quartus Prime Version	21.2
Letsatsi la ho nšoa	2021.06.23

GPIO Intel FPGA IP Features

GPIO IP ea mantlha e kenyelletsa likarolo tse tšehetsang li-block tsa I / O tsa sesebelisoa. U ka sebelisa Intel Quartus Prime parameter editor ho lokisa GPIO IP core.

GPIO IP ea mantlha e fana ka likarolo tsena:

• Habeli data rate input/output (DDIO)—karolwana ya dijithale e menahaneng kapa e fokotsang lebelo la data la kanale ya dikgokahano.
• Liketane tsa ho lieha - lokisa liketane tsa ho lieha ho etsa tieho e itseng le ho thusa ho koala nako ea I / O.
• Li-buffers tsa I/O-hokela lipampiri ho FPGA.

GPIO Intel FPGA IP Data Litsela

Setšoantšo sa 1. Boemo bo phahameng View ea GPIO ea Qetello e le 'Ngoe

Letlapa la 2. GPIO IP Core Data Path Mekhoa

Mokhoa oa data	Register Mode
	Bypass	Ngoliso e Bonolo	DDR I/O
			Sekhahla se Feletseng	Half-Rate
Kenyeletso	Lintlha li tloha karolong ea ho lieha ho ea ho mantlha, li feta li-I/Os (DDIO) kaofela tse habeli.	DDIO ea boleng bo felletseng e sebetsa joalo ka rejisetara e bonolo, e feta li-DDIO tsa halofo. The Fitter e khetha hore na e tla paka rejisetara ho I/O kapa e kenye tšebetsong rejisetara motheong oa eona, ho latela sebaka le nako ea khoebo.	DDIO e felletseng e sebetsa joalo ka DDIO e tloaelehileng, e feta li-DDIO tsa halofo.	DDIO e felletseng e sebetsa joalo ka DDIO e tloaelehileng. Li-DDIO tsa sekhahla sa halofo li fetolela data ea sekhahla se felletseng ho data ea sekhahla sa halofo.
Sephetho	Lintlha li tloha ho mantlha ho ea ho karolo ea ho lieha, ho feta li-DDIO tsohle.	DDIO ea boleng bo felletseng e sebetsa joalo ka rejisetara e bonolo, e feta li-DDIO tsa halofo. The Fitter e khetha hore na e tla paka rejisetara ho I/O kapa e kenye tšebetsong rejisetara motheong oa eona, ho latela sebaka le nako ea khoebo.	DDIO e felletseng e sebetsa joalo ka DDIO e tloaelehileng, e feta li-DDIO tsa halofo.	DDIO e felletseng e sebetsa joalo ka DDIO e tloaelehileng. Li-DDIO tsa sekhahla sa halofo li fetolela data ea sekhahla se felletseng ho data ea sekhahla sa halofo.
Ho iketsetsa liqeto	Buffer ea tlhahiso e khanna phini ea tlhahiso le buffer ea ho kenya.	DDIO e felletseng e sebetsa joalo ka rejisetara e bonolo. Buffer ea tlhahiso e khanna phini ea tlhahiso le buffer ea ho kenya.	DDIO e felletseng e sebetsa joalo ka DDIO e tloaelehileng. Buffer ea tlhahiso e khanna phini ea tlhahiso le buffer ea ho kenya. Buffer ea ho kenya e khanna lihlopha tse tharo tsa li-flip-flops.	DDIO e felletseng e sebetsa joalo ka DDIO e tloaelehileng. Li-DDIO tsa sekhahla sa halofo li fetolela data e felletseng ho ea halofo. Buffer ea tlhahiso e khanna phini ea tlhahiso le buffer ea ho kenya. Buffer ea ho kenya e khanna lihlopha tse tharo tsa li-flip-flops.

Haeba u sebelisa matshwao a hlakileng a asynchronous le a seng a setilwe, di-DDIO kaofela di arolelana matshwao ana a tshwanang.

Li-DDIO tsa lebelo le felletseng li hokela lioacheng tse arohaneng. Ha o sebelisa li-DDIO tsa lebelo le felletseng, oache e felletseng e tlameha ho sebetsa habeli ho feta halofo ea sekhahla. U ka sebelisa likamano tse fapaneng tsa mekhahlelo ho fihlela litlhoko tsa nako.

Lintlha Tse Amanang
Li-Bits tsa Libese le Tse Tsoang Holimo le Tlase leqepheng la 12

Mokhoa oa ho Kena

Pedi e romella data ho buffer ea ho kenya, 'me buffer ea ho kenya e fepa karolo ea ho lieha. Kamora hore data e fihle ho tlhahiso ea elemente ea ho lieha, "programmable bypass multiplexers" e khetha likarolo le litsela tse tla sebelisoa.tagea li-DDIO, tse felletseng le tse halofo.

Setšoantšo sa 2. E Nolofalitsoeng View ea Mokhoa o le Mong oa ho Kena oa GPIO

1. Letlapa le fumana data.
2. DDIO IN (1) e hapa lintlha tse mabapi le ho phahama le ho theoha ha ck_fr le ho romela lintlha, matšoao (A) le (B) ka setšoantšo se latelang sa waveform, ka tekanyo e le 'ngoe ea data.
3. DDIO IN (2) le DDIO IN (3) li fokotsa sekhahla sa data ka halofo.
4. dout[3:0] e hlahisa data joalo ka bese ea lebelo la halofo.

Setšoantšo sa 3. Input Path Waveform ho DDIO Mode e nang le Half-Rate Conversion

Palong ena, data e tloha ho nako e felletseng ka sekhahla sa data habeli ho isa ho halofo ea sekhahla ka sekhahla sa data se le seng. Sekhahla sa data se arotsoe ka tse 'nè' me boholo ba libese bo eketsoa ka karolelano e tšoanang. Phallo e akaretsang ka GPIO IP core e lula e sa fetohe.

Kamano ea 'nete ea nako lipakeng tsa matšoao a fapaneng e ka fapana ho latela moralo, tieho, le mekhahlelo eo u e khethang bakeng sa lioache tse felletseng le tse halofo.

Tlhokomeliso: Mokotla oa GPIO IP ha o tšehetse ho lekoa ka matla ha li-pin tsa bidirectional. Bakeng sa lits'ebetso tse hlokang ho feto-fetoha ha li-pin tsa bidirectional, sheba lintlha tse amanang.

Lintlha Tse Amanang

• PHY Lite for Parallel Interfaces Intel FPGA IP Core User Guide: Intel Stratix 10, Intel Arria 10, le Intel Cyclone 10 GX Devices
  E fana ka tlhaiso-leseling e batsi bakeng sa lits'ebetso tse hlokang OCT e matla bakeng sa li-pin tsa bidirectional.
• Sephetho le Sephetho Lumella Litsela leqepheng la 7

Output le Output Numella Litsela

Karolo ea ho lieha ha tlhahiso e romella data ho pad ka buffer ea tlhahiso.

Tsela e 'ngoe le e' ngoe ea tlhahiso e na le s tse pelitagea li-DDIO, tse halofong le tse felletseng.

Setšoantšo sa 4. E Nolofalitsoeng View ea Mokhoa o le Mong oa Tlhahiso ea GPIO

Setšoantšo sa 5. Output Path Waveform ho DDIO Mode e nang le Half-Rate Conversion

Setšoantšo sa 6. E Nolofalitsoeng View ea Output nolofalletsa Tsela

Phapang pakeng tsa tsela ea tlhahiso le tsela ea tlhahiso e nolofalletsang (OE) ke hore tsela ea OE ha e na DDIO e feletseng. Ho ts'ehetsa lits'ebetso tsa ngoliso e pakiloeng tseleng ea OE, rejisetara e bonolo e sebetsa joalo ka DDIO e felletseng. Ka lebaka le tšoanang, ke DDIO e le 'ngoe feela ea halofo ea sekhahla e teng.

Tsela ea OE e sebetsa ka mekhoa e meraro e latelang:

• Bypass — mantlha e romella data ka kotloloho ho karolo ea ho lieha, e feta li-DDIO tsohle.
• Registeri e Pakiloeng—e feta DDIO ea halofo ea sekhahla.
• SDR e hlahisoang ka sekhahla-halofo ea DDIOs e fetolela data ho tloha ho tekanyo e feletseng ho ea ho halofo.

Tlhokomeliso: Mokotla oa GPIO IP ha o tšehetse ho lekoa ka matla ha li-pin tsa bidirectional. Bakeng sa lits'ebetso tse hlokang ho feto-fetoha ha li-pin tsa bidirectional, sheba lintlha tse amanang.

Lintlha Tse Amanang

• PHY Lite for Parallel Interfaces Intel FPGA IP Core User Guide: Intel Stratix 10, Intel Arria 10, le Intel Cyclone 10 GX Devices
  E fana ka tlhaiso-leseling e batsi bakeng sa lits'ebetso tse hlokang OCT e matla bakeng sa li-pin tsa bidirectional.
• Mokhoa oa ho Kena leqepheng la 5

GPIO Intel FPGA IP Interface Signals

Ho ipapisitse le litlhophiso tsa parametha tseo u li boletseng, matšoao a fapaneng a sebopeho a teng bakeng sa GPIO IP core.

Setšoantšo sa 7. GPIO IP Core Interfaces

Setšoantšo sa 8. Lipontšo tsa GPIO Interface

Letlapa la 3. Lipontšo tsa Pad Interface

Sebopeho sa pad ke khokahano ea 'mele ho tloha ho GPIO IP core ho ea pad. Khokahano ena e ka ba sebopeho sa ho kenya, se hlahisoang kapa sa bidirectional, ho ipapisitse le tlhophiso ea mantlha ea IP. Tafoleng ena, SIZE ke bophara ba data bo boletsoeng ho IP core paramethara.

Lebitso la Letshwao	Tataiso	Tlhaloso
pad_in[SIZE-1:0]	Kenyeletso	Letšoao la ho kenya ho tsoa ho pad.
pad_in_b[SIZE-1:0]	Kenyeletso	Node e fosahetseng ea lets'oao le fapaneng la ho kenya letsoho ho tsoa ho pad. Boema-kepe bona boa fumaneha haeba u bulela Sebelisa buffer e fapaneng kgetho.
pad_out[SIZE-1:0]	Sephetho	Letšoao la tlhahiso ho pad.
pad_out_b[SIZE-1:0]	Sephetho	Node e mpe ea lets'oao le fapaneng la tlhahiso ho pad. Boema-kepe bona boa fumaneha haeba u bulela Sebelisa buffer e fapaneng kgetho.
pad_io[SIZE-1:0]	Ho iketsetsa liqeto	Khokahano ea lets'oao la mahlakore a mabeli le pad.
pad_io_b[SIZE-1:0]	Ho iketsetsa liqeto	Node e mpe ea khokahano ea lets'oao le fapaneng la bidirectional le pad. Boema-kepe bona boa fumaneha haeba u bulela Sebelisa buffer e fapaneng kgetho.

Letlapa la 4. Lipontšo tsa Interface tsa Data

Sebopeho sa data ke sebopeho sa ho kenya kapa se hlahisoang ho tloha ho GPIO IP core ho ea ho FPGA core. Tafoleng ena, SIZE ke bophara ba data bo boletsoeng ho IP core parameter editor.

Lebitso la Letshwao	Tataiso	Tlhaloso
din[DATA_SIZE-1:0]	Kenyeletso	Kenyelletso ea data ho tsoa ho konokono ea FPGA ka mokhoa oa tlhahiso kapa oa bidirectional. DATA_SIZE e ipapisitse le mokhoa oa ho ingolisa: Bypass kapa ngoliso e bonolo—DATA_SIZE = SIZE DDIO ntle le halofo ea tekanyo—DATA_SIZE = 2 × SIZE DDIO e nang le maikutlo a halofo—DATA_SIZE = 4 × SIZE
lerata[DATA_SIZE-1:0]	Sephetho	Tlhahiso ea data ho mantlha ea FPGA ka mokhoa oa ho kenya kapa oa bidirectional, DATA_SIZE e ipapisitse le mokhoa oa ho ingolisa: Bypass kapa ngoliso e bonolo—DATA_SIZE = SIZE DDIO ntle le halofo ea tekanyo—DATA_SIZE = 2 × SIZE DDIO e nang le maikutlo a halofo—DATA_SIZE = 4 × SIZE
oe[OE_SIZE-1:0]	Kenyeletso	Kenyelletso ea OE ho tsoa ho mantlha ea FPGA ka mokhoa oa tlhahiso ka Dumella sephetho se bulelang port butswe, kapa mokgwa wa mahlakore a mabedi. OE e sebetsa holimo. Ha o fetisetsa data, seta lets'oao lena ho 1. Ha o amohela data, beha lets'oao lena ho 0. OE_SIZE e ipapisitse le mokhoa oa ho ngolisa: Bypass kapa ngoliso e bonolo—DATA_SIZE = SIZE DDIO ntle le halofo ea tekanyo—DATA_SIZE = SIZE DDIO e nang le maikutlo a halofo—DATA_SIZE = 2 × SIZE

Letlapa la 5. Lipontšo tsa Sehokelo sa Oache

Sehokelo sa oache ke sehokelo sa oache ea ho kenya. E na le matshwao a fapaneng, ho itshetlehile ka tlhophiso. GPIO IP ea mantlha e ka ba le lioache tsa zero, e le 'ngoe, tse peli kapa tse' nè. Likou tsa oache li hlaha ka tsela e fapaneng litlhophisong tse fapaneng ho bonts'a ts'ebetso ea 'nete e etsoang ke lets'oao la oache.

Lebitso la Letshwao	Tataiso	Tlhaloso
ck	Kenyeletso	Litselang tsa ho kenya le ho tsoa, ​​oache ena e fepa rejisetara e pakiloeng kapa DDIO ha o tima Half Rate logic paramethara. Ka mokhoa oa bidirectional, oache ena ke oache e ikhethang bakeng sa litsela tsa ho kenya le ho tsoa ha u tima Arola lioache tsa ho kenya/liphetho paramethara.
ck_fr	Kenyeletso	Litselang tsa ho kenya le ho tsoa, ​​lioache tsena li fepa li-DDIO tsa sekhahla se felletseng le halofo haeba u bulela Half Rate logic paramethara. Ka mokhoa oa bidirectional, litsela tsa ho kenya le ho tsoa li sebelisa lioache tsena haeba u tima Arola lioache tsa ho kenya/liphetho paramethara.
ck_hr
ck_ka	Kenyeletso	Ka mokhoa oa mahlakore a mabeli, lioache tsena li fepa rejisetara e pakiloeng kapa DDIO mekhoeng ea ho kenya le ho tsoa ha u totobatsa litlhophiso tsena ka bobeli: Tima the Half Rate logic paramethara. Bulela Arola lioache tsa ho kenya/liphetho paramethara.
ck_out
ck_fr_in	Kenyeletso	Ka mokhoa oa mahlakore a mabeli, lioache tsena li fepa DDIOS ea tekanyo e feletseng le halofo ka litsela tsa ho kenya le ho hlahisa haeba u totobatsa litlhophiso tsena ka bobeli. Bulela Half Rate logic paramethara. Bulela Arola lioache tsa ho kenya/liphetho paramethara. Bakeng sa mohlalaample, ck_fr_out e fepa DDIO e felletseng tseleng ea tlhahiso.
ck_fr_out
ck_hr_in
ck_hr_out
cke	Kenyeletso	Oache e nolofalletsa.

Lethathamo la 6. Lipontšo tsa Interface Interface

Sebopeho sa ho felisa se kopanya GPIO IP core ho li-buffers tsa I / O.

Lebitso la Letshwao	Tataiso	Tlhaloso
seriesterminationcontrol	Kenyeletso	Kena ho tsoa ho "termination control block" (OCT) ho ea ho buffers. E beha boleng ba letoto la buffer ea impedance.
parallelterminationcontrol	Kenyeletso	Kena ho tsoa ho "termination control block" (OCT) ho ea ho buffers. E beha boleng ba "buffer parallel impedance value".

Letlapa la 7. Reset Lipontšo tsa Sehokelo

Sebopeho sa reset se kopanya GPIO IP core ho DDIOs.

Lebitso la Letshwao	Tataiso	Tlhaloso
sclr	Kenyeletso	Keno e hlakileng ea synchronous. Ha e fumanehe haeba o lumella sset.
aclr	Kenyeletso	Kenyelletso e hlakileng ea Asynchronous. E sebetsang holimo. Ha e fumanehe haeba o lumella aset.
aset	Kenyeletso	Asynchronous set input. E sebetsang holimo. Ha e fumanehe haeba o lumella aclr.
sset	Kenyeletso	Kenyelletso ea sete e lumellanang. Ha e fumanehe haeba o nolofalletsa sclr.

Lintlha Tse Amanang
Li-Bits tsa Libese le Tse Tsoang Holimo le Tlase leqepheng la 12

Lipontšo tse arolelanoang

• Kenyelletso, tlhahiso, le litsela tsa OE li arolelana matšoao a tšoanang a hlakileng le a seng a setiloe.
• Sephetho le tsela ea OE li arolelana matšoao a oache a tšoanang.

Data Bit-Order for Data Interface

Setšoantšo sa 9. Kopano ea Data Bit-Order

Palo ena e bonts'a kopano ea tatellano e nyane bakeng sa matšoao a data a din, doout le oe.

• Haeba boleng ba bese ea data e le SIZE, LSB e maemong a nepahetseng haholo.
• Haeba boleng ba bese ea data ke 2 × SIZE, bese e entsoe ka mantsoe a mabeli a SIZE.
• Haeba boholo ba bese ea data bo le 4 × SIZE, bese e entsoe ka mantsoe a mane a SIZE.
• LSB e boemong bo nepahetseng ho fetisisa ba lentsoe ka leng.
• Lentsoe le nepahetseng haholo le bolela lentsoe la pele le hlahang bakeng sa libese tse hlahisoang le lentsoe la pele le hlahang bakeng sa libese tse kenang.

Lintlha Tse Amanang
Mokhoa oa ho Kena leqepheng la 5

Li-Bits tsa Libese tse Kenang le Tse Tsoang Holimo le Tlase

Li-bits tse phahameng le tse tlaase ka lipontšo tsa ho kenya kapa tse hlahisoang li kenyelelitsoe ka har'a libese tsa ho kenya le ho hlahisa li-din le dout.

Bese e Kenang

Bakeng sa libese tsa din, haeba datain_h le datain_l e le li-bits tse phahameng le tse tlase, bophara ka bong e le datain_width:

• datain_h = din[(2 × datain_width – 1):datain_width]
• datain_l = din[(datain_width – 1):0]

Bakeng sa mohlalaample, bakeng sa din[7:0] = 8'b11001010:

• datain_h = 4'b1100
• datain_l = 4'b1010

Bese e hlahisoang

Bakeng sa bese ea dout, haeba dataout_h le dataout_l e le li-bits tse phahameng le tse tlase, bophara ka bong e le dataout_width:

• dataout_h = dout[(2 × dataout_width – 1):dataout_width]
• dataout_l = dout[(dataout_width – 1):0]

Bakeng sa mohlalaample, bakeng sa dout[7:0] = 8'b11001010:

• dataout_h = 4'b1100
• dataout_l = 4'b1010

Lipontšo tsa Interface ea Data le Lioache tse Tšoanang

Letlapa la 8. Lipontšo tsa Interface ea Data le Lioache tse Tšoanang

Lebitso la Letshwao	Tlhophiso ea Parameter			Tshupanako
	Register Mode	Half Rate	Lioache tse arohaneng
din	Ngoliso e Bonolo DDIO	E tima	E tima	ck
	DDIO	On	E tima	ck_hr
	Ngoliso e Bonolo DDIO	E tima	On	ck_ka
	DDIO	On	On	ck_hr_in
qeaqea oe	Ngoliso e Bonolo DDIO	E tima	E tima	ck
	DDIO	On	E tima	ck_hr
	Ngoliso e Bonolo DDIO	E tima	On	ck_out
	DDIO	On	On	ck_hr_out
sclr sset Lipontšo tsohle tsa pad	Ngoliso e Bonolo DDIO	E tima	E tima	ck
	DDIO	On	E tima	ck_fr
	Ngoliso e Bonolo DDIO	E tima	On	Mokhoa oa ho kenya: ck_in Tsela ea ho tsoa: ck_out
	DDIO	On	On	Mokhoa oa ho kenya: ck_fr_in Tsela ea ho tsoa: ck_fr_out

Ho netefatsa Tšebeliso ea Mehloli le Ts'ebetso ea Moralo

U ka sheba litlaleho tsa Intel Quartus Prime compilation ho fumana lintlha tse mabapi le tšebeliso ea lisebelisoa le ts'ebetso ea moralo oa hau.

1. Ho menu, tobetsa Ho sebetsa ➤ Qala ho Kopanya ho tsamaisa pokello e felletseng.
2. Ka mor'a ho hlophisa moralo, tobetsa Ho sebetsa ➤ Tlaleho ea ho Kopanya.
3. Ho sebelisa the Tafole ea likateng, leba ho Fitter ➤ Karolo ea Mohloli.
   a. Ho view tlhahisoleseling ea tšebeliso ea lisebelisoa, khetha Kakaretso ea Tšebeliso ea Mehloli.
   b. Ho view tlhahisoleseling ea tšebeliso ea lisebelisoa, khetha Tšebeliso ea Mehloli ke Mokhatlo.

GPIO Intel FPGA IP Parameter Litlhophiso

U ka seta litlhophiso tsa paramethara bakeng sa GPIO IP core ho software ea Intel Quartus Prime. Ho na le lihlopha tse tharo tsa likhetho: Kakaretso, Buffer, le Ngoliso.

Letlapa la 9. GPIO IP Core Parameters - Kakaretso

Paramethara	Boemo	Maemo a lumelletsoeng	Tlhaloso
Tataiso ea Lintlha	—	Kenyeletso Sephetho  Bidir	E hlalosa tataiso ea data bakeng sa GPIO.
Bophara ba data	—	1 ho ea ho 128	E hlalosa bophara ba data.
Sebelisa mabitso a boema-kepe a maemo a holimo a fetileng	—	On E tima	Sebelisa mabitso a boema-kepe a tšoanang le a lisebelisoa tsa Stratix V, Arria V, le Cyclone V. Bakeng sa mohlalaample, dout e fetoha dataout_h le dataout_l, mme din e fetoha datain_h le datain_l. Tlhokomeliso: Boitšoaro ba likou tsena bo fapane le ba lisebelisoa tsa Stratix V, Arria V, le Cyclone V. Bakeng sa tataiso ea ho falla, sheba lintlha tse amanang.

Letlapa la 10. GPIO IP Core Parameters - Buffer

Paramethara	Boemo	Maemo a lumelletsoeng	Tlhaloso
Sebelisa buffer e fapaneng	—	On  E tima	Ha e buletsoe, e nolofalletsa li-buffers tsa I/O tse fapaneng.
Sebelisa pseudo differential buffer	Tataiso ea Lintlha = Sephetho Sebelisa phapang ea buffer = Buletsoe	On  E tima	Haeba e buletsoe ka mokhoa oa tlhahiso, e nolofalletsa li-buffers tsa pseudo differential. Khetho ena e buletsoe ka bo eona bakeng sa mokhoa oa bidirectional ha o ka bulela Sebelisa buffer e fapaneng.
Sebelisa potoloho ea libese	Data Direction = Input kapa Bidir Sebelisa phapang ea buffer = Off	On  E tima	Ha e buletsoe, sebaka sa ho ts'oara libese se ka khona ho ts'oara lets'oao ho pini ea I/O sebakeng sa eona sa ho qetela moo buffer state e tla ba 1 kapa 0 empa e se ts'ireletso e phahameng.
Sebelisa tlhahiso e bulehileng ea drain	Data Direction = Output kapa Bidir Sebelisa phapang ea buffer = Off	On  E tima	Ha e buletsoe, tlhahiso e bulehileng e nolofalletsa sesebelisoa ho fana ka matšoao a taolo ea boemo ba sistimi joalo ka ho sitisa le ho ngola, ho nolofalletsa matshwao a ka hlahisoang ke lisebelisoa tse ngata ho sistimi ea hau.
Dumella sephetho se bulelang port	Tataiso ea Lintlha = Sephetho	On  E tima	Haeba e buletsoe, e nolofalletsa mosebelisi ho kenya boema-kepe ba OE. Khetho ena e buletsoe ka bo eona bakeng sa mokhoa oa bidirectional.
Lumella li-port tsa "seriestermination / paralleltermination".	—	On  E tima	Ha e laetilwe, e dumella "seriesterminationcontrol" le "parallelterminationcontrol ports" ea buffer ea tlhahiso.

Letlapa la 11. GPIO IP Core Parameters - Registers

Paramethara	Boemo	Maemo a lumelletsoeng	Tlhaloso
Ngolisa mokhoa	—	Ha ho letho  Ngoliso e bonolo  DDIO	E hlalosa mokhoa oa ho ngolisa GPIO IP core: Ha ho letho-e totobatsa khokahano e bonolo ea terata ho tloha/ho ea ho buffer. Ngoliso e bonolo-e hlalosa hore DDIO e sebelisoa e le rejisetara e bonolo ka mokhoa o le mong oa sekhahla sa data (SDR). The Fitter e ka paka rejisetara ena ho I/O. DDIO- e hlalosa hore IP core e sebelisa DDIO.
Numella boema-kepe bo hlakileng ba synchronous / preset	Mokhoa oa ho ngolisa = DDIO	Ha ho letho  Hlakileng  Seta pele	E hlalosa mokhoa oa ho kenya ts'ebetsong boema-kepe bo bocha ba synchronous. Ha ho letho-E tima boema-kepe ba ho seta botjha. Hlakileng- E nolofalletsa boema-kepe ba SCLR bakeng sa ho hlakola ka mokhoa o lumellanang. Seta pele-E nolofalletsa boema-kepe ba SSET bakeng sa ho seta esale pele.
Numella boema-kepe bo hlakileng ba asynchronous / preset	Mokhoa oa ho ngolisa = DDIO	Ha ho letho  Hlakileng  Seta pele	E hlalosa mokhoa oa ho kenya ts'ebetsong boema-kepe ba asynchronous reset. Ha ho letho- E tima boema-kepe bo bocha ba asynchronous. Hlakileng- E nolofalletsa boema-kepe ba ACLR bakeng sa ho hlakola ha asynchronous. Seta pele-E nolofalletsa boema-kepe ba ASET bakeng sa ho seta esale pele. Lipontšo tsa ACLR le ASET li holimo.
Lumella likou tsa oache	Mokhoa oa ho ngolisa = DDIO	On  E tima	On-e pepesa boema-kepe ba oache (CKE) ho u lumella ho laola ha data e koetsoe kapa e tsoa. Letšoao lena le thibela data ho fetisoa ntle le taolo ea hau. E tima- Boema-kepe ba ho nolofalletsa oache ha bo senoloe mme data e lula e feta ka har'a rejistara ka bo eona.
Half Rate logic	Mokhoa oa ho ngolisa = DDIO	On  E tima	Ha e buletsoe, e lumella DDIO ea halofo ea sekhahla.
Arohane input / output Clocks	Tataiso ea data = Bidir  Mokhoa oa ho ngolisa = Ngoliso e bonolo kapa DDIO	On  E tima	Ha e buletsoe, e lumella lioache tse arohaneng (CK_IN le CK_OUT) bakeng sa litsela tsa ho kenya le ho tsoa ka mokhoa oa mahlakore a mabeli.

Lintlha Tse Amanang

• Li-Bits tsa Libese le Tse Tsoang Holimo le Tlase leqepheng la 12
• Tataiso: Fapanyetsana datain_h le datain_l Ports ho IP e Faletseng leqepheng la 23

Ngolisa Packing

GPIO IP ea mantlha e u lumella ho paka ngoliso sebakeng sa periphery ho boloka sebaka le tšebeliso ea lisebelisoa.

O ka hlophisa DDIO ea tekanyo e felletseng tseleng ea ho kenya le ea tlhahiso joalo ka flip flop. Ho etsa joalo, kenya .qsf mesebetsi e thathamisitsoeng tafoleng ena.

Letlapa la 12. Ngolisa Ho Paka Likabelo tsa QSF

Tsela	Mosebetsi oa QSF
Ho paka ngoliso ea lintho	QSF Kabelo set_instance_assignment -lebitso FAST_INPUT_REGISTER ON -ho
Sephutheloana sa ho paka	set_instance_assignment -lebitso FAST_OUTPUT_REGISTER ON -to
Output nolofalletsa registara paka	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -ho

Tlhokomeliso: Likabelo tsena ha li fane ka tiiso ea ho pakela ngoliso. Leha ho le joalo, likabelo tsena li thusa Fitter ho fumana sebaka sa molao. Ho seng joalo, Fitter e boloka flip flop bohareng.

GPIO Intel FPGA IP Nako

Ts'ebetso ea mantlha ea GPIO IP e ipapisitse le litšitiso tsa I / O le mekhahlelo ea oache. Ho netefatsa nako ea tlhophiso ea GPIO ea hau, Intel e khothaletsa hore u sebelise Analyzer ea Nako.

Lintlha Tse Amanang
Intel Quartus Prime Timing Analyzer

Likarolo tsa Nako

Likarolo tsa nako ea mantlha tsa GPIO IP li na le litsela tse tharo.

• Litsela tsa I/O - ho tloha ho FPGA ho ea ho lisebelisoa tsa kantle tse amohelang le ho tloha lisebelisoa tsa ho fetisetsa kantle ho FPGA.
• Litsela tsa mantlha tsa data le oache - ho tloha ho I/O ho ea mantlha le ho tloha mantlha ho ea ho I/O.
• Litsela tsa phetisetso—ho tloha ho sekhahla ho isa ho sekhahla se felletseng sa DDIO, le ho tloha ho sekhahla se felletseng ho isa ho halofo ea DDIO.

Tlhokomeliso: Time Analyzer e tšoara tsela e ka hare ho li-block tsa DDIO_IN le DDIO_OUT e le mabokose a matšo.

Setšoantšo sa 10. Likarolo tsa Nako ea ho Kena ea Tsela ea ho Kena

Setšoantšo sa 11. Likarolo tsa Nako ea Nako ea Output

Setšoantšo sa 12. Sephetho se Nontsha Likarolo Tsa Nako ea Tsela

Lintho tsa ho lieha

Software ea Intel Quartus Prime ha e ipehele likarolo tsa ho lieha ho etsa hore ho be bonolo ho hlahloba nako ea I/O. Ho koala nako kapa ho holisa ho thella, beha likarolo tsa ho lieha ka letsoho ho li-setting tsa Intel Quartus Prime file (.qsf).

Lethathamo la 13. Likabelo tsa ho lieha .qsf

Hlakisa mesebetsi ena ho .qsf ho fihlella likarolo tsa tieho.

Teeho Element	.qsf Mosebetsi
Kenyelletso ea Teeho	set_instance_assignment to -lebitso INPUT_DELAY_CHAIN ​​<0..63>
Karolo ea ho lieha ho hlahisoa	set_instance_assignment to -lebitso OUTPUT_DELAY_CHAIN ​​<0..15>
Output Noble Delay Element	set_instance_assignment to -lebitso OE_DELAY_CHAIN ​​<0..15>

Tlhahlobo ea Nako

Software ea Intel Quartus Prime ha e hlahise lithibelo tsa nako ea SDC bakeng sa GPIO IP core. O tlameha ho kenya lithibelo tsa nako ka bowena.

Latela litataiso tsa nako le mohlalaampho etsa bonnete ba hore Mohlahlobi oa Nako o sekaseka nako ea I/O ka nepo.

• Ho etsa tlhahlobo e nepahetseng ea nako bakeng sa litsela tsa li-interface tsa I/O, hlakisa litšitiso tsa boemo ba sistimi ea li-pin tsa data khahlano le phini ea oache ea sistimi ho .sdc. file.
• Ho etsa tlhahlobo e nepahetseng ea nako bakeng sa litsela tsa mantlha, hlalosa litlhophiso tsena tsa oache ho .sdc file:
  — Oache ho lirejisetara tsa mantlha
  - E shebe lirejiseteng tsa I/O bakeng sa rejisetara e bonolo le mekhoa ea DDIO

Lintlha Tse Amanang
AN 433: Ho khina le ho hlahlobisisa li-interface tsa Mohloli-Synchronous
E hlalosa mekhoa ea ho thibela le ho sekaseka lihokelo tse lumellanang le mohloli.

Ngoliso e le 'Ngoe ea Kenyelletso ea Sekhahla sa Lintlha

Setšoantšo sa 13. Ngoliso e le 'ngoe ea Chelete ea Boitsebiso

Letlapa la 14. Ngoliso e le 'Ngoe ea Kenyelletso ea Lebelo la Lintlha .sdc Taelo Examples

Taelo	Laela Example	Tlhaloso
theha_clock	create_clock -name sdr_in_clk -period "100 MHz" sdr_in_clk	E etsa litlhophiso tsa oache bakeng sa oache e kenang.
set_input_tieho	set_input_delay -clock sdr_in_clk 0.15 sdr_in_data	E laela Sehlahlobi sa Nako ho sekaseka nako ea ho kenya I/O ka ho lieha ho kenya 0.15 ns.

Ngoliso ea Kenyelletso ea DDIO e Felletseng kapa ea Halofo

Lehlakore la ho kenya la rejisetara ea DDIO ea sekhahla se felletseng le halofo ea sekhahla ea tšoana. U ka hatella sistimi ka nepo ka ho sebelisa oache ea sebele ho etsa mohlala oa transmitter ea off-chip ho FPGA.

Setšoantšo sa 14. Ngoliso ea Input ea DDIO e Felletseng kapa ea Halofo

Letlapa la 15. Kakaretso e Felletseng kapa Half-Rate DDIO Input Register .sdc Command Examples

Taelo	Laela Example	Tlhaloso
theha_clock	create_clock -name virtual_clock - nako "200 MHz" create_clock -name ddio_in_clk -nako "200 MHz" ddio_in_clk	Etsa litlhophiso tsa oache bakeng sa oache ea sebele le oache ea DDIO.
set_input_tieho	set_input_delay -clock virtual_clock 0.25 ddio_in_data set_input_delay -add_delay -clock_fall -clock virtual_clock 0.25 ddio_in_data	Laela Mohlahlobi oa Nako hore a hlahlobe moeli oa oache o nepahetseng le moeli o mobe oa phetisetso. Hlokomela -add_delay taelong ea bobeli ea set_input_delay.
beha_tsela_ea_mashano	seta_tsela_ea_mashano -wela_ho tloha virtual_clock -rise_to ddio_in_clk set_false_path -hlaha_ho tloha virtual_clock -fall_to ddio_in_clk	Laela Mohlahlobi oa Nako hore a hlokomolohe moeli oa oache o nepahetseng ho registara e hlahisitsoeng e mpe, le moeli oa oache o mobe ho registara e hlahisitsoeng. Tlhokomeliso: Maqhubu a ck_hr e tlameha ho ba halofo ea maqhubu a ck_fr. Haeba I/O PLL e khanna lioache, u ka nahana ho sebelisa taelo ea deive_pll_clocks .sdc.

Rejistara e le 'Ngoe ea Sephetho sa Data Rate

Setšoantšo sa 15. Ngoliso e le 'ngoe ea Sephetho sa Data Rate

Letlapa la 16. Ngoliso e le 'Ngoe ea Phatlalatso ea Sekhahla sa Data .sdc Taelo Examples

Taelo	Laela Example	Tlhaloso
create_clock and create_generated_clock	create_clock -name sdr_out_clk - nako "100 MHz" sdr_out_clk create_generated_clock -source sdr_out_clk -name sdr_out_outclk sdr_out_outclk	Hlahisa oache ea mohloli le oache e hlahisoang ho fetisa.
set_output_ delay	set_output_delay -clock sdr_out_clk 0.45 sdr_out_data	E laela Timing Analyzer ho sekaseka lintlha tse hlahisoang ho li fetisetsa khahlano le oache e hlahisoang hore e fetisetsoe.

Rekoto e Felletseng kapa ea Halofo ea DDIO ea Liphetho

Lehlakore la sephetho sa lirejisete tsa DDIO tsa sekhahla se felletseng le halofo li tšoana.

Letlapa la 17. DDIO Output Register .sdc Taelo Examples

Taelo	Laela Example	Tlhaloso
create_clock and create_generated_clock	create_clock -name ddio_out_fr_clk -nako "200 MHz" ddio_out_fr_clk create_generated_clock -source ddio_out_fr_clk -lebitso ddio_out_fr_outclk ddio_out_fr_outclk	Hlahisa lioache ho DDIO le oache hore e fetisetsoe.
set_output_ delay	set_output_delay -clock ddio_out_fr_outclk 0.55 ddio_out_fr_data set_output_delay -add_delay -hora_hoetla -hora ddio_out_fr_outclk 0.55 ddio_out_fr_data	Laela Timing Analyzer ho sekaseka lintlha tse ntle le tse mpe khahlano le nako ea tlhahiso.
beha_tsela_ea_mashano	set_false_path -hlaha_ho tloha ddio_out_fr_clk -fall_to ddio_out_fr_outclk seta_tsela_ea_mashano -wela_ho tloha ddio_out_fr_clk -rise_to ddio_out_fr_outclk	Laela Timing Analyzer ho iphapanyetsa moeli o nyolohang oa oache ea mohloli khahlano le moeli o oelang oa oache e tsoang, le moeli o oelang oa oache ea mohloli khahlano le moeli o ntseng o phahama oa oache e tsoang.

Litaelo tsa ho Koala Nako

Bakeng sa lirejistara tsa ho kenya tsa GPIO, phetisetso ea I/O ea ho kenya e kanna ea hloleha ho boloka nako haeba u sa behe ketane ea ho lieha ho kenya. Ho hloleha hona ho bakoa ke tieho ea oache e kholo ho feta tieho ea data.

Ho fihlella nako ea ho ts'oara, eketsa tieho tseleng ea ho kenya data u sebelisa ketane ea ho lieha ho kenya. Ka kakaretso, ketane ea ho lieha ho kenya e ka ba 60 ps ka mohato ho 1 lebelo la lebelo. Ho fumana sebaka sa ho lieha ho kenya nako ho fetisa nako, arola "negative hold slack" ka 60 ps.

Leha ho le joalo, haeba I/O PLL e khanna lioache tsa lirejistara tsa ho kenya tsa GPIO (rejisetara e bonolo kapa mokhoa oa DDIO), o ka seta mokhoa oa matšeliso ho mokhoa oa ho tsamaisana. Fitter e tla leka ho hlophisa I/O PLL bakeng sa ho seta hantle le ho ts'oara monyebe bakeng sa tlhahlobo ea nako ea I/O.

Bakeng sa tlhahiso le tlhahiso ea GPIO li nolofalletsa lirekoto, o ka eketsa ho lieha ho data ea tlhahiso le oache o sebelisa tlhahiso le tlhahiso e nolofalletsang liketane tsa ho lieha.

• Haeba o bona tlolo ea nako ea ho seta, o ka eketsa tlhophiso ea ketane ea ho lieha ha nako ea tlhahiso.
• Haeba o bona tlolo ea nako ea ho ts'oara, o ka eketsa tlhophiso ea ketane ea ho lieha ha data.

GPIO Intel FPGA IP Design Examples

GPIO IP ea mantlha e ka hlahisa moralo oa example hore e tsamaellane le tlhophiso ea hau ea IP ho mohlophisi oa paramethara. U ka sebelisa li-design tsena tsa exampjoalo ka litšupiso tsa ho tiisa motheo oa IP le boits'oaro bo lebelletsoeng ho papisong.

O ka hlahisa sebopeho sa exampho tsoa ho mohlophisi oa parameter ea GPIO IP. Ka mor'a hore u behe li-parameter tseo u li batlang, tobetsa Hlahisa Example Design. IP core e hlahisa sebopeho sa example mohloli files bukeng eo u e boletseng.

Setšoantšo sa 16. Mohloli Files ho Moetso o Hlahisitsoeng Example Directory

Tlhokomeliso: The .qsys files ke tsa tšebeliso ea ka hare nakong ea moralo example moloko feela. Ha o khone ho fetola tsena .qsys files.

GPIO IP Core Synthesizable Intel Quartus Prime Design Example

Moetso o entsoeng example ke sistimi e lokiselitsoeng ho kopanya Platform Designer eo o ka e kenyelletsang morerong oa Intel Quartus Prime.

Ho Hlahisa le ho Sebelisa Moralo Example

Ho hlahisa moralo o hlophisitsoeng oa Intel Quartus Prime example tsoa mohloling files, tsamaisa taelo e latelang ho moralo oa mohlalaample directory:

quartus_sh -t make_qii_design.tcl

Ho hlakisa sesebelisoa se nepahetseng seo u ka se sebelisang, tsamaisa taelo e latelang:

quartus_sh -t make_qii_design.tcl [lebitso_la sesebelisoa]

Sengoliloeng sa TCL se theha bukana ea qii e nang le morero oa ed_synth.qpf file. U ka bula le ho bokella morero ona ho Intel Quartus Prime software.

GPIO IP Core Simulation Design Example

Moqapi oa ketsiso exampLe sebelisa litlhophiso tsa paramethara ea hau ea GPIO IP ho aha mohlala oa IP o hokahaneng le mokhanni oa papiso. Mokhanni o hlahisa sephethephethe se sa reroang mme o hlahloba ka hare ho molao oa data e tsoang.

Ho sebelisa moralo example, o ka tsamaisa papiso o sebelisa taelo e le 'ngoe, ho latela simulator eo o e sebelisang. Papiso e bonts'a mokhoa oa ho sebelisa GPIO IP core.

Ho Hlahisa le ho Sebelisa Moralo Example

Ho hlahisa moralo oa ketsiso example tsoa mohloling files bakeng sa simulator ea Verilog, tsamaisa taelo e latelang ho moralo oa mohlalaample directory:

quartus_sh -t make_sim_design.tcl

Ho hlahisa moralo oa ketsiso example tsoa mohloling files bakeng sa simulator ea VHDL, tsamaisa taelo e latelang ho moralo oa example directory:

quartus_sh -t make_sim_design.tcl VHDL

Sengoloa sa TCL se theha bukana ea sim e nang le li-subdirectories-e le 'ngoe bakeng sa sesebelisoa se seng le se seng se tšehetsoeng sa papiso. U ka fumana mangolo bakeng sa sesebelisoa se seng le se seng sa papiso ho li-directory tse tsamaellanang.

Phallo ea Phallo ea IP bakeng sa Arria V, Cyclone V, le Stratix V Devices

Phallo ea phalliso ea IP e u lumella ho falla ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, le ALTIOBUF IP cores ea lisebelisoa tsa Arria V, Cyclone V, le Stratix V ho ea ho GPIO IP core ea lisebelisoa tsa Intel Arria 10 le Intel Cyclone 10 GX.

Phallo ena ea phalliso ea IP e lokisa GPIO IP core ho tsamaisana le litlhophiso tsa ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, le ALTIOBUF IP cores, e u lumellang ho nchafatsa motheo oa IP.

Tlhokomeliso: Li-cores tse ling tsa IP li tšehetsa phallo ea phalliso ea IP ka mekhoa e ikhethileng feela. Haeba setsi sa hau sa IP se le ka mokhoa o sa tšehetsoeng, ho ka 'na ha hlokahala hore u tsamaise IP Parameter Editor bakeng sa GPIO IP core le ho lokisa IP core ka letsoho.

E fallisa ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, le ALTIOBUF IP Cores

Ho fallisetsa ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, le ALTIOBUF IP cores ho GPIO Intel FPGA IP IP core, latela mehato ena:

1. Bula ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, kapa ALTIOBUF IP ea hau ea mantlha ho IP Parameter Editor.
2. Ho Lelapa la lisebelisoa tse khethiloeng hajoale, khetha Intel Arria 10 or Intel Leholiotsoana 10 GX.
3. Tobetsa Qetella ho bula GPIO IP Parameter Editor.
   IP Parameter Editor e lokisa litlhophiso tsa mantlha tsa GPIO IP tse tšoanang le tsa mantlha tsa ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, kapa ALTIOBUF.
4. Haeba ho na le li-setting life kapa life tse sa lumellaneng lipakeng tsa tse peli, khetha li-setting tse ncha tse tšehelitsoeng.
5. Tobetsa Qetella ho nchafatsa motheo oa IP.
6. Kenya sebaka sa hau sa mantlha sa ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, kapa ALTIOBUF IP ho RTL ka GPIO IP core.

Tlhokomeliso: Mabitso a boema-kepe a GPIO IP a kanna a se ts'oane le mabitso a boema-kepe a ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, kapa ALTIOBUF IP. Ka hona, ho fetola feela lebitso la mantlha la IP hanghang ho kanna ha se lekane.

Lintlha Tse Amanang
Li-Bits tsa Libese le Tse Tsoang Holimo le Tlase leqepheng la 12

Tataiso: Fapanyetsana datain_h le datain_l Ports ho IP e Fallang

Ha o tlosa GPIO IP ea hau ho tloha lisebelisoa tse fetileng ho ea ho GPIO IP core, o ka bulela Sebelisa mabitso a boema-kepe a maemo a holimo a fetileng khetho ho GPIO IP core parameter editor. Leha ho le joalo, boitšoaro ba likou tsena ho GPIO IP core bo fapane le ba IP cores e sebelisetsoang lisebelisoa tsa Stratix V, Arria V, le Cyclone V.

GPIO IP ea mantlha e tsamaisa likou tsena ho li-registe tse hlahisoang lithakong tsena tsa oache:

• datain_h—ka lehlakoreng le holimo la outclock
• datain_l - moeling o oelang oa outclock

Haeba u falletse GPIO IP ea hau ho tsoa ho lisebelisoa tsa Stratix V, Arria V, le Leholiotsoana V, fetola datain_h le datain_l ports ha u tiisa IP e hlahisoang ke GPIO IP core.

Lintlha Tse Amanang
Li-Bits tsa Libese le Tse Tsoang Holimo le Tlase leqepheng la 12

GPIO Intel FPGA IP User Guide Archives

Liphetolelo tsa IP li tšoana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihla ho v19.1. Ho tsoa ho Intel Quartus Prime Design Suite software version 19.2 kapa hamorao, li-cores tsa IP li na le morero o mocha oa phetolelo ea IP.

Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.

IP Core Version	Bukana ea Mosebelisi
20.0.0	GPIO Intel FPGA IP User Guide: Intel Arria 10 le Intel Cyclone 10 GX Devices
19.3.0	GPIO Intel FPGA IP User Guide: Intel Arria 10 le Intel Cyclone 10 GX Devices
19.3.0	GPIO Intel FPGA IP User Guide: Intel Arria 10 le Intel Cyclone 10 GX Devices
18.1	GPIO Intel FPGA IP User Guide: Intel Arria 10 le Intel Cyclone 10 GX Devices
18.0	GPIO Intel FPGA IP User Guide: Intel Arria 10 le Intel Cyclone 10 GX Devices
17.1	Intel FPGA GPIO IP Core User Guide
17.0	Altera GPIO IP Core User Guide
16.1	Altera GPIO IP Core User Guide
16.0	Altera GPIO IP Core User Guide
14.1	Altera GPIO Megafunction User Guide
13.1	Altera GPIO Megafunction User Guide

Nalane ea Tokomane ea Tokomane bakeng sa Tataiso ea Mosebelisi ea GPIO Intel FPGA IP: Intel Arria 10 le Intel Cyclone 10 GX Devices

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
2021.07.15	21.2	20.0.0	E ntlafalitse setšoantšo se bonts'ang tse nolofalitsoeng view ea GPIO e phethiloeng e le 'ngoe ea ho kenya letsoho ho nchafatsa dout[0] to dout[3] le dout[3] to dout[0].
2021.03.29	21.1	20.0.0	E ntlafalitse nomoro ea mofuta oa GPIO IP ho 20.0.0.
2021.03.12	20.4	19.3.0	E ntlafalitse tataiso ea phalliso ea IP ho hlakisa hore GPIO IP e khanna datain_h moeling o nyolohang le datain_l pheletsong e oelang.
2019.10.01	19.3	19.3.0	Ho lokisitsoe phoso ea mongolo ho likhoutu tsa kabelo tsa .qsf sehloohong se mabapi le likarolo tsa tieho.
2019.03.04	18.1	18.1	Lihloohong tse mabapi le tsela ea ho kenya, 'me tlhahiso le tlhahiso li nolofalletsa litsela: E lokisitse lintlha lihloohong ho hlakisa hore GPIO Intel FPGA IP ha e tšehetse tlhophiso e matla ea lipini tsa mahlakore a mabeli. Lihokelo tse kentsoeng ho PHY Lite bakeng sa Parallel Interfaces Intel FPGA IP Core User Guide: Intel Stratix 10, Intel Arria 10, le Intel Cyclone 10 GX Devices bakeng sa tlhaiso-leseling e batsi mabapi le lits'ebetso tse hlokang ho lekoa ho matla bakeng sa liphini tse peli.
2018.08.28	18.0	18.0	E rehiloe tokomane ho tsoa ho Intel FPGA GPIO IP Core User Guide ho GPIO Intel FPGA IP User Guide: Intel Arria 10 le Intel Cyclone 10 GX Devices. E kentse sehokelo ho tataiso ea mosebelisi ea Intel Stratix 10 GPIO IP.  E reha IP hape ho tloha "Intel FPGA GPIO" ho "GPIO Intel FPGA IP".  Maemo a lokisitsoeng a "clk_fr" le "clk_hr" ho "ck_fr" le "ck_hr".  E ntlafalitse tsela ea ho kenya ea GPIO IP le litšoantšo tsa litsela tse hlahisoang ho bonts'a mabitso a matšoao a mantlha a IP.

Letsatsi	Phetolelo	Liphetoho
La 2017 Pulungoana XNUMX	2017.11.06	Tšehetso e ekelitsoeng bakeng sa lisebelisoa tsa Intel Cyclone 10 GX. E ntlafalitse mabitso a matšoao ka lipalo ho tsamaisana le mabitso a matšoao ho GPIO IP core. E kenyellelitse mokhoa oa ho hlahisa waveform. E rehiloe "Altera GPIO IP core" ho "Intel FPGA GPIO IP core". E rehiloe "Altera IOPLL IP core" ho "Intel FPGA IOPLL IP core". E rehiloe "TimeQuest Time Analyzer" ho "Timing Analyzer". E rehiloe "Qsys" ho "Moetsi oa Platform". E hlakisitse hore matšoao a ASET le ACLR a sebetsa holimo.
Motšeanong 2017	2017.05.08	E ntlafalitse tafole e thathamisang liparamente tsa buffer tsa GPIO ho hlakisa maemo a Sebelisa potoloho ea libese khetho ea parameter. E fetoletsoe joalo ka Intel.
Mphalane 2016	2016.10.31	E ntlafalitse mokhoa oa ho kenya letsoho. E kentse sehlooho se hlalosang li-bits tse phahameng le tse tlase libese tsa din le dout.
Phato 2016	2016.08.05	Lintlha tse kenyellelitsoeng mabapi le tšehetso e matla ea OCT ho GPIO IP core. E ntlafalitse sehlooho mabapi le litlhophiso tsa liparamente ho ntlafatsa ho nepahala le ho hlaka. E ntlafalitse karolo e mabapi le ho hlahisa sebopeho sa example. E kentse taba ea tataiso mabapi le boitšoaro ba likou tsa lefa ha u fallela ho GPIO IP core ho tloha lisebelisoa tsa Stratix V, Arria V, le Cyclone V. Ngola hape le ho hlophisa bocha tokomane ho ntlafatsa ho hlaka le ho nolofalloa ho e sebelisa. Maemo a fetotsoeng a Quartus II ho Quartus Prime.
Phato 2014	2014.08.18	Boitsebiso ba nako bo kentsoeng. Tlhahisoleseding ea ho paka ea rejisetara e ekelitsoeng. E kentsoe Sebelisa mabitso a boema-kepe a maemo a holimo a fetileng paramethara. Ena ke parameter e ncha. Tlhahisoleseding ea ho paka ea rejisetara e ekelitsoeng. E fetotse lentsoe megafunction ka IP core.
La 2013 Pulungoana XNUMX	2013.11.29	Tokollo ea pele.

Romella Maikutlo

GPIO Intel FPGA IP User Guide: Intel Arria 10 le Intel Cyclone 10 GX Devices

Litokomane / Lisebelisoa

Intel GPIO Intel FPGA IP [pdf] Bukana ea Mosebelisi GPIO Intel FPGA IP, GPIO, Intel FPGA IP, FPGA IP

Litšupiso

• Bukana ea Mosebelisi