Intel E-Series 5 GTS Transceiver

Litlhaloso

• Lebitso la Sehlahisoa: GTS Transceiver Dual Simplex Interfaces
• Nomoro ea mohlala: 825853
• Letsatsi la Phatlalatso: 2025.01.24/XNUMX

Tlhahisoleseding ya Sehlahiswa

Li-transceivers tsa GTS ho Agilex 5 FPGAs li ts'ehetsa lits'ebetso tse fapaneng tsa protocol tse bonolo. Ka mokhoa oa simplex, mocha oa GTS ha o tsoe ka tsela e le 'ngoe, o siea mochine o sa sebelisoeng kapa moamoheli. Ka ho sebelisa dual simplex mode, o ka sebelisa mocha o sa sebelisoeng ho kenya tšebetsong protocol e 'ngoe e ikemetseng ea simplex.

Selelekela

Tataiso ena ea mosebelisi e hlalosa mokhoa oa ho kenya tšebetsong mokhoa oa dual simplex (DS) ho li-transceivers tsa Agilex™ 5 GTS.

Dual simplex mode e bua ka mokhoa oa ts'ebetso oa mocha oa transceiver oa GTS moo o ka behang mochine o ikemetseng le moamoheli ea ikemetseng mocheng o le mong oa transceiver, ka hona o eketsa tšebeliso ea lisebelisoa tsa transceiver ho Agilex 5 FPGAs. Buka ea mosebelisi e hlalosa:

• Li-IP tsa protocol tsa simplex tse tšehelitsoeng ka mokhoa oa dual simplex
• Mokhoa oa ho rala li-interfaces tse peli tsa simplex pele u qala moralo oa hau
• Mokhoa oa ho kenya tšebetsong phallo e habeli ea moralo oa simplex

U ka kenya tšebetsong mofuta oa dual simplex ho Quartus® Prime Pro Edition software version 24.2 ho ea pele.

Lintlha Tse Amanang

• GTS Transceiver PHY Bukana ea Mosebelisi
• GTS SDI II Intel FPGA IP User Guide
• GTS SDI II Intel FPGA IP Design Example Bukana ea Mosebelisi
• GTS HDMI Intel FPGA IP User Guide
• GTS HDMI Intel FPGA IP Design Example Bukana ea Mosebelisi
• GTS DisplayPort PHY Altera FPGA IP User Guide
• GTS JESD204C Intel FPGA IP User Guide
• GTS JESD204C Intel FPGA IP Design Example Bukana ea Mosebelisi
• GTS JESD204B Intel FPGA IP User Guide
• GTS JESD204B Intel FPGA IP Design Example Bukana ea Mosebelisi
• GTS Serial Lite IV Intel FPGA IP User Guide
• GTS Serial Lite IV Intel FPGA IP Design Example Bukana ea Mosebelisi
• Tataiso ea Mosebelisi ea Quartus Prime Pro Edition: Moetso oa Moqapi

© Altera Corporation. Altera, logo ea Altera, letšoao la 'a', le matšoao a mang a Altera ke matšoao a Altera Corporation. Altera le Intel warrant performance ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Altera kapa Intel ha e sebetsa, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Altera le Intel ha ba nke boikarabelo kapa melato e hlahang ts'ebelisong kapa ts'ebelisong ea tlhaiso-leseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka hore e ngoloe ke Altera kapa Intel. Bareki ba Altera le Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.

Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

Fetileview

Li-transceivers tsa GTS ho Agilex 5 FPGAs li ts'ehetsa lits'ebetso tse fapaneng tsa protocol tse bonolo. Ka mokhoa oa simplex, mocha oa GTS ha o tsoe ka tsela e le 'ngoe 'me o siea mochine o sa sebelisoeng kapa moamoheli. U sebelisa mokhoa oa dual simplex, u ka sebelisa transmitter e sa sebelisoeng kapa mocha oa moamoheli ho kenya tšebetsong protocol e 'ngoe e ikemetseng ea simplex joalo ka ha ho bonts'itsoe setšoantšong se latelang.

Mokhoa oa dual simplex (DS) o tšehetsa motsoako o latelang oa simplex protocol IPs(1).

Letlapa la 1. Likopano tsa IP tsa Protocol tse tšehelitsoeng bakeng sa Dual Simplex Mode

IP ea moamoheli	Phetiso ea IP
	SDI	HDMI	DisplayPort	SeriLite IV	JESD204C	JESD204B
SDI	Ee	Ee	Ee	Che	Che	Che
HDMI	Ee	Ee	Ee	Che	Che	Che
DisplayPort	Ee	Ee	Ee	Che	Che	Che
SeriLite IV	Che	Che	Che	Ee	Ee(2)	Ee(2)
JESD204C	Che	Che	Che	Ee(2)	Ee	Ee(2)
JESD204B	Che	Che	Che	Ee(2)	Ee(2)	Ee

Mokhoa oa DS o ka kengoa ts'ebetsong software ea Quartus Prime Pro Edition ka ho hlahisa DS IP e ipapisitseng le li-IP tsa protocol tse bonolo, le ho sebelisa DS IP bakeng sa moralo oa RTL joalo ka ha ho totobalitsoe setšoantšong se latelang. DS IP e hlahisitsoeng e na le li-IP tsa motho ka mong tseo u batlang ho li kopanya ka mokhoa oa DS le ho li sebelisa moralong oa hau.

1. Mokhoa oa DS o tšehetsoa feela bakeng sa liprothokholo tse boletsoeng tsa simplex, eseng bakeng sa mekhoa e tloaelehileng ea TX/RX e nang le GTS PMA/FEC Direct PHY Intel FPGA IP (ntle le ha parameter ea melao ea tlhophiso ea PMA e behiloe ho SDI kapa HDMI).
2. Motsoako ona oa mokhoa oa DS ha o tšehetsoe tokollong ea hajoale ea software ea Quartus Prime Pro Edition.

1. Phetoho efe kapa efe kapa ntlafatso ea mofuta ho li-IP tsa simplex protocol tseo u li sebelisang phallong ea DS li hloka hore DS IP e nchafatsoe.
2. Haeba u sa hloke mokhoa oa DS, mohato ona ha o sebetse.
3. Haeba o sa hloke mokhoa oa DS, hokela simplex IP ka kotloloho moetsong oa hau.
4. U ka etsisa DS IP ka mor'a Analysis le Elaboration.

Kutloisiso le ho Rala li-interface tsa Dual Simplex

Pele o qala ka ts'ebetsong ea mokhoa oa DS, etsa qeto le ho rera li-IP tsa simplex (transmitter le receiver) tseo u batlang ho li beha mocha o le mong oa transceiver. Haeba li-IP tsa simplex moralong oa hau ha ho hlokahale hore li behoe mocheng o le mong oa transceiver, phallo ea mokhoa oa DS e hlalositsoeng tokomaneng ena ha e sebetse 'me u ka tsoela pele ho kopanya li-IP tsa simplex ka ho toba moralong oa hau oa RTL.

Ho na le lihlopha tse peli tsa li-IP tsa protocol tse ka tšehetsang mokhoa oa DS:

• SDI, HDMI le DisplayPort
• SerialLite IV, JESD204C le JESD204B
  • Ha u khetha li-IP tsa protocol tse tšehetsoeng bakeng sa mokhoa oa DS, rera hore na li-IP tsa hau tsa simplex li penta joang (transmitter le receiver ka mocha o le mong) ho pholletsa le liteishene tse sebelisoang. Mothating ona, moralo o ipapisitse le ho beoa ha mocha ka mokhoa o utloahalang ho theha Sehlopha sa DS seo u ka se sebelisang hamorao bakeng sa tlhahiso ea DS IP. U ka etsa mosebetsi oa ho beha phini ka mor'a moloko oa IPtage.
  • E latelang exampe bonts'a mokhoa oa ho rala li-IP tsa simplex ka mokhoa oa DS ho theha Sehlopha sa DS. Sehlopha sa DS se hlalosoa e le sehlopha sa li-IP tsa simplex tse nang le bonyane mocha o le mong ka mokhoa oa DS.

Example 1: Transmitter e le 'ngoe ea SDI e Kopantsoeng le Moamoheli a le Mong oa SDI
Ho sena mohlalaample, transmitter e le 'ngoe ea SDI e kopantsoe le moamoheli a le mong oa SDI ho theha sehlopha sa DS joalo ka ha ho bonts'itsoe setšoantšong se latelang.

Example 2: Transmitter e le 'ngoe ea HDMI e Kopantsoeng le Moamoheli o le Mong oa HDMI
Ho sena mohlalaample, e 'ngoe ea HDMI transmitter e tsamaisana le seamoheli se le seng sa HDMI ho theha sehlopha sa DS joalo ka ha ho bonts'itsoe setšoantšong se latelang. O ka beha moamoheli oa HDMI ho likanale 0-2 kapa likanale 1-3.

Example 3: E 'ngoe ea HDMI Transmitter e Kopantsoeng le Li-Receivers tse peli tsa SDI le SDI Transmitter
Ho sena mohlalaample, HDMI transmitter e le 'ngoe e kopantsoe le ba amohelang SDI tse peli ho theha sehlopha sa DS hammoho le transmitter e le 'ngoe ea SDI e sa sebetseng joalokaha ho bontšitsoe setšoantšong se latelang. Ka mokhoa o utloahalang, o ka beha li-receptors tse peli tsa SDI libakeng tse fapaneng ha feela li kopane le liteishene tsa transmitter tsa HDMI. Kaha transmitter ea SDI ha e kopane le IP e 'ngoe e bonolo, ha se karolo ea sehlopha sa DS (o ke ke oa e kenyelletsa sehlopheng sa DS) mme ha e hloke phallo ea DS.

Ha u rera pairing ea hau ea simplex IP bakeng sa mokhoa oa DS, u tlameha ho nahana ka tse latelang:

• TX bonding placement-leha ho bokana ho ipapisitse le ho beoa ka mokhoa o utloahalang, li-IP tsa li-channel transmitter tse ngata li hloka tlamahano, 'me li tlameha ho fihlela litlhoko tsa ho beoa ha mocha joalokaha ho hlalositsoe ho Channel Placement for PMA Direct Configuration for Bonded Lane Aggregation palo ea GTS Transceiver PHY User Guide.
• Same System PLL bakeng sa TX le RX-Li-IP tse bonolo tse pentiloeng ka mokhoa oa DS tse sebelisang mokhoa oa ho koala oa PLL li tlameha ho sebelisa System PLL e tšoanang bakeng sa mocha oo. Li-IP tsa Simplex tse sebelisang mokhoa oa ho koala oa PMA li ka kopanngoa feela le IP e 'ngoe e bonolo e nang le mokhoa oa oache oa PMA. Mokhoa oa ho tsamaisa oache oa PMA le mokhoa oa PLL oa sistimi ka har'a kanale ha o tšehetsoe.
• Tšebeliso ea FEC bakeng sa TX le RX-Li-IP tse bonolo tse pentiloeng ka mokhoa oa DS bakeng sa mocha li tlameha ho ba le maemo a tšoanang a FEC (e ka ba a lumelloa kapa a sa sebelisoe). Bakeng sa mohlalaample, haeba u na le GTS SerialLite IV IP TX e nang le FEC e nolofalitsoeng, u ka e kopanya feela le GTS SerialLite IV IP RX e nang le FEC e lumelletsoeng.
• phihlello ya segokanyimmediamentsi sa Avalon® ya memori- transmitter le moamoheli ba arolelana segokanyimmediamentsi sa mohopolo oa Avalon ho fihlella mocha ka mong. Ha li-IP tsa simplex li pentiloe ka mokhoa oa DS, DS IP e hlahisitsoeng e kenyelletsa sebopeho sa Avalon-mapped interface se bolokang sebopeho sa mohopolo oa IP Avalon le moamoheli oa IP Avalon-mapped interface. Sena se tšoana le ha o sa sebelise mokhoa oa DS.

Ho kenya tšebetsong li-interface tsa Dual Simplex

Khaolo ena e hlalosa ts'ebetsong e 'meli e bonolo e thehiloeng ho example 2 ho Understanding and Planning Dual Simplex Interfaces khaolo. Ts'ebetsong ea DS e kopanya HDMI protocol simplex TX le simplex RX empa ka litekanyetso tse fapaneng tsa tlhophiso.

Ho hlahisa Simplex IP
U tlameha ho qala ka ho theha le ho hlahisa IP e 'ngoe le e' ngoe ea simplex ka thoko ka ho latela tataiso e khethehileng ea IP.

Hlokomela:

• Bakeng sa SDI, o tlameha ho theha IP e bonolo ka paramente ea Both Base le PHY e khethiloeng bakeng sa khetho ea SDI_II wrapper ho GTS SDI II Intel FPGA IP.
• Bakeng sa HDMI, o tlameha ho theha IP ea simplex ka HDMI le Transceiver parameter e khethiloeng bakeng sa khetho ea HDMI wrapper ho GTS HDMI Intel FPGA IP.
• Bakeng sa DisplayPort, o tlameha ho theha IP e bonolo o sebelisa GTS DisplayPort PHY Altera FPGA IP.
• Bakeng sa JESD204C, o tlameha ho theha IP e bonolo ka Bobeli Base le PHY kapa PHY Feela paramethara e khethiloeng bakeng sa khetho ea wrapper ea JESD204C ho GTS JESD204C Intel FPGA IP.
• Bakeng sa JESD204B, o tlameha ho theha IP e bonolo ka Bobeli Base le PHY kapa PHY Feela paramethara e khethiloeng bakeng sa khetho ea wrapper ea JESD204B ho GTS JESD204B Intel FPGA IP.
• Bakeng sa Serial Lite IV, o tlameha ho theha IP e bonolo ka ho khetha khetho ea Rx kapa Tx bakeng sa paramethara ea mokhoa oa PMA. Bakeng sa RS-FEC, o tlameha ho nolofalletsa paramethara ea Enable RS-FEC hape u nolofalletse RS-FEC ho nolofalloa ho se seng sa Serial Lite IV Simplex IP e behiloeng ka har'a parameter e le 'ngoe tlas'a konopo ea Simplex Merging ho IP tab.

Ho hlahisa HDMI simplex IP, latela mehato ena:

1. Theha HDMI simplex TX IP le HDMI simplex RX IP ka ho khetha paramethara ea HDMI le Transceiver le likarolo tse ling tse amanang le moralo oa hau u sebelisa GTS HDMI Intel FPGA IP.
2. Hlahisa IP files bakeng sa HDMI simplex IPs ka ho tobetsa mohato oa IP Generation ho Compilation Dashboard of Quartus Prime Pro Edition software joalokaha ho bontšitsoe setšoantšong se latelang.

Hang ha moloko oa IP o phethela ka katleho, mohato oa IP Generation o fetoha o motala ka letšoao le haufi le oona joalokaha ho bontšitsoe setšoantšong se latelang.

Lintlha Tse Amanang

• GTS HDMI Intel FPGA IP User Guide
• GTS SDI II Intel FPGA IP User Guide
• GTS DisplayPort PHY Altera FPGA IP User Guide
• GTS JESD204C Intel FPGA IP User Guide
• GTS JESD204C Intel FPGA IP Design Example Bukana ea Mosebelisi
• GTS JESD204B Intel FPGA IP User Guide
• GTS JESD204B Intel FPGA IP Design Example Bukana ea Mosebelisi
• GTS Serial Lite IV Intel FPGA IP User Guide
• GTS Serial Lite IV Intel FPGA IP Design Example Bukana ea Mosebelisi

Ho sebelisa Dual Simplex Assignment Editor
U ka sebelisa sesebelisoa sa DS Assignment Editor ho hlophisa le ho bona ts'ebetsong ea DS ho latela litlhophiso tsa banka le mocha. Karolo ena e akaretsa feela mehato ea ho sebelisa sesebelisoa sa DS Assignments Editor ka ho khetheha bakeng sa ts'ebetsong ea DS e hlalositsoeng bukeng ena ea mosebedisi.

Hlokomela:
Sheba HSSI Dual Simplex IP Generation Flow in Quartus Prime Pro Edition User Guide: Design Compilation bakeng sa lintlha tse eketsehileng.

Ho sebelisa DS Assignment Editor ho abela lihlopha tsa DS le ho boloka likabelo tse peli tse bonolo, latela mehato ena:

1. Tobetsa Mosebetsi > Dual Simplex (DS) Assignment Editor ho software ea Quartus Prime Pro Edition. DS Assignment Editor e bula lethathamo la li-IP tse peli tse bonolo tse tšehelitsoeng moralong oa hau Lethathamong la IP le likabelo life kapa life tse teng tsa DS tlasa DS Groups. Ho sena mohlalaample, lifensetere li thathamisa li-IP tsa HDMI TX le HDMI RX joalokaha ho bontšitsoe setšoantšong se latelang.
   Hlokomela: DS Assignment Editor e bontša feela li-IP tsa simplex tse tšehetsoeng ke DS.
2. Fesetereng ea DS Assignment Editor, tobetsa ka ho le letona mohlala oa hdmi_rx tlas'a IP List, 'me u tobetse Create Instance In> New DS Group joalokaha ho bontšitsoe setšoantšong se latelang. Sena se theha sehlopha se secha sa DS se bitsoang DS_GROUP_0 mme se eketsa mohlala oa hdmi_rx fenstereng ea DS Groups.
3. E latelang, tobetsa ka ho le letona setšoantšo sa hdmi_tx tlas'a IP List, 'me u tobetse Create Instance In> DS_GROUP_0 joalokaha ho bontšitsoe setšoantšong se latelang. Sena se eketsa mohlala oa hdmi_tx fenstereng ea DS Groups e entsoeng mohatong o fetileng.
4. Sebono se fenstereng e ka letsohong le letona la fensetere ea DS Assignment Editor se bonts'a DS_GROUP_0 joalo ka ha ho bonts'itsoe setšoantšong se latelang. Karolo e ka tlase e ka letsohong le letšehali e bonts'a Lihlopha tsa DS mme e bonts'a hore hdmi_rx e thehiloe joalo ka
   hdmi_rx_inst0 le hdmi_tx e thehiloe joalo ka hdmi_tx_inst0. Ha ho hlokahala, o ka reha bocha maemo a DS_GROUP_0, hdmi_rx_inst0, le hdmi_tx_inst0 ka ho tobetsa habedi mabitso a mabitso a hlahisitsweng setšoantšong se latelang. Ntle le moo, o ka fetola sebaka sa mohlala ka ho nchafatsa boemo ba Relative Offset ka likarolo tsa likanale. U ka boela ua lumella Mokhoa oa Loopback ka mokhoa o fumanehang ho lopolla mokhoa oa ho lokisa bothata.
5. Haeba moralo oa hau o hloka oache e arolelanoang lipakeng tsa mefuta ea RX simplex le TX simplex, o ka nolofalletsa karolo ea Shared Clock ka ho khetha IP e 'ngoe le e 'ngoe e kentsoeng fenstereng ea DS_GROUP_0 ebe o tobetsa Lebokose la ho hlahloba Clock e arolelanoeng joalokaha ho bontšitsoe setšoantšong se latelang. Joale u ka khetha sebaka sa oache ho tloha ho IP Port drop down menu 'me u fane ka lebitso le lecha la boema-kepe lebokoseng la Merged Port.|
   Hlokomela: Ho na le likou tse itseng feela tsa oache tse fumanehang bakeng sa ho kopanngoa ho itšetlehileng ka protocol ea IP. U tlameha ho hlahloba le ho netefatsa hore na u ka kopanya likou tsa oache pele u tsoela pele ho etsa mohato ona.
6. Ho boloka likabelo tsa DS, tobetsa Boloka Likabelo ebe u tobetsa OK fensetereng e hlahang.
   

Ha o boloka likabelo tsa DS, li eketsoa ka bo eona morerong .qsf file joalo ka ha ho bontšitsoe setšoantšong se latelang.

Ho hlahisa Dual Simplex IP
Karolo ena e hlalosa mehato ea ho hlahisa sehlopha sa "dual simplex" se entsoeng nakong e fetileng (DS_GROUP_0) ho DS Assignment Editor.

Ho etsa dual simplex IP le ho hlahloba litlaleho, latela mehato ena:

1. Tobetsa HSSI Dual Simplex IP Generation ho Dashboard ea Compilation ea software ea Quartus Prime Pro Edition joalokaha ho bontšitsoe setšoantšong se latelang. Software pele e tsamaisa mohato oa IP Generation ebe e tsamaisa mohato oa HSSI Dual Simplex IP Generation.
2. Tobetsa konopo ea Open Compilation Report haufi le mohato oa HSSI Dual Simplex IP Generation ho fihlella DS IP e tlaleha hore software ea Quartus Prime Pro Edition joalo ka ha ho bonts'itsoe setšoantšong se latelang. Ho hlahisa DS IP ka katleho ho bontšoa ka letšoao.
3. Review Tlaleho ea Kabelo ea Mosebelisi (Tlaleho ea Mohlophisi oa Kabelo ea DS) le Tlaleho ea Dual Simplex IP e tlaleha hore software ea Quartus Prime Pro Edition e hlahisa joalo ka ha ho bonts'itsoe lipalong tse latelang.

Ho kopanya Dual Simplex IP

• Karolo ena e hlalosa mehato ea ho hokahanya IP e entsoeng ka bobeli e bonolo ho moralo oa hau.
• Moralo o hloka hore GTS Reset Sequencer Intel FPGA IP le GTS System PLL Clocks Intel FPGA IP e sebetse ka nepo, ka hona li-IP ka bobeli li tlameha ho netefatsoa le ho hokahana le DS IP.

Ho hokela dual simplex IP, latela mehato ena:

1. Software ea Quartus Prime Pro Edition e bonts'a DS IP le li-IP tse bonolo sebakeng sa Project Navigator joalokaha ho bontšitsoe setšoantšong se latelang.Ho view mojule oa boemo bo holimo oa DS IP, eketsa DS_GROUP_0.qip file ebe o tobetsa DS_GROUP_0.sv SystemVerilog file joalokaha ho bontšitsoe setšoantšong se latelang. Software ea Quartus Prime Pro Edition e hlahisa The DS IP port interface ho DS_GROUP_0.sv SystemVerilog. file. DS_GROUP_0.sv file e boloka likou tsohle e le li-IP tsa simplex hape e kopanya likou tse amanang le sequencer ea reset le system PLL (haeba e sebelisoa) joalo ka ha ho bonts'itsoe lipalong tse latelang.
2. E latelang, kenya mojule oa DS IP moralong oa hau oa boemo bo holimo file 'me u etse likhokahano tse hlokahalang ho latela litlhoko tsa moralo oa hau joalo ka ha ho bonts'itsoe setšoantšong se latelang.

Ho netefatsa Ts'ebetso ea Dual Simplex IP
Karolo ena e hlalosa mehato ea ho kopanya le ho netefatsa IP e hokahaneng ea "dual simplex IP" moralong oa hau.

Ho kopanya le ho netefatsa dual simplex IP, latela mehato ena:

1. Kopanya moralo ka ho tsamaisa mohato oa Analysis & Synthesis ho Quartus Prime Pro Edition software Compilation Dashboard. Setšoantšo se latelang se bontša dashboard ka mor'a hore ho be le tlhahlobo e atlehileng ea Analysis & Synthesis.
2. O ka netefatsa DS IP ka papiso ha o qetile ka katleho Analysis & Synthesis. Setšoantšo se latelang se bontša example ea DS IP e fetang ketsiso le HDMI testbench.
   Hlokomela: U ka etsisa DS IP ka mor'a Analysis & Elaboration stage phethela.
3. Beha phini bakeng sa moralo. Ho software ea Quartus Prime Pro Edition, tobetsa Mesebetsi > Pin Planner ho bula sesebelisoa sa pin planner. Beha lithapo tsa RX le TX bankeng e le 'ngoe ho kopanya simplex TX le simplex RX pins ho mocha o le mong oa 'mele (bakeng sa ex.ample Bank 4C) joalokaha ho bontšitsoe setšoantšong se latelang.
4. Etsa pokello e felletseng ea ts'ebetsong ea moralo oa DS joalo ka ha ho bonts'itsoe setšoantšong se latelang.
5. Hang ha pokello e phethiloe ka katleho, u ka sheba sebaka sa ho beoa ha moralo ka ho tobetsa Fitter> Plan> Open Compilation Report mohato oa Quartus Prime Pro Edition software Compilation Dashboard joalokaha ho bontšitsoe setšoantšong se latelang.

Joale u ka netefatsa hore software ea Quartus Prime Pro Edition e behile li-pins tsa simplex TX le simplex RX ho latela litlhophiso tsa Pin Planner le lithakhisa li kopantsoe ka katleho ka ho hlahloba litlaleho joalokaha ho bontšitsoe lipalo-palo tse latelang.

Nalane ea Phetoho ea Litokomane bakeng sa Tataiso ea Mosebelisi ea GTS Transceiver Dual Simplex

Tokomane Version	Quartus Prime Version	Liphetoho
2025.01.24	24.3.1	O entse liphetoho tse latelang: Ho ekelitsoe likhokahano tsa tataiso ea basebelisi ba Serial Lite IV le JESD204B khaolong ea Selelekela. E ntlafalitse Tafole e Tšehetsoeng ea Protocol IP bakeng sa Dual Simplex Mode tafole ho Overview khaolo e nang le tlhaiso-leseling ea tšehetso ea JESD204C. E ntlafalitse karolo ea Kutloisiso le Moralo oa Dual Simplex Interfaces ka tlhahisoleseling mabapi le maemo a FEC ka mokhoa oa DS. E ntlafalitse molaetsa ho Hlahisa karolo ea Simplex IP ka GTS JESD204B Intel FPGA IP le GTS Serial Lite IV litlhoko tsa litlhophiso tsa Intel FPGA IP bakeng sa mokhoa oa simplex. E ntlafalitse karolo ea Ho Sebelisa Karolo ea Dual Simplex Assignment Editor ka mohato o eketsehileng oa ho sebelisa oache e arolelanoang pakeng tsa mekhoa ea RX simplex le TX simplex. E ntlafalitse setšoantšo sa DS_GROUP_0.sv Reset Sequencer le System PLL Ports Interface ho karolo ea Ho Hokela ha Dual Simplex IP.
2024.10.07	24.3	O entse liphetoho tse latelang: E kenyellelitsoe likhokahano ho litataiso tsa basebelisi tsa JESD204C khaolong ea Selelekela. E ntlafalitse Tafole e Tšehetsoeng ea Protocol IP bakeng sa Dual Simplex Mode tafole ho Overview khaolo e nang le tlhaiso-leseling ea tšehetso ea JESD204C. E ntlafalitse molaetsa ho Hlahisa karolo ea Simplex IP ka litlhoko tsa litlhophiso tsa GTS JESD204C Intel FPGA IP bakeng sa mokhoa oa simplex.
2024.08.19	24.2	Tokollo ea pele.

LBH

P: Na nka sebelisa mekhoa ea tloaelo ea TX/RX ka GTS PMA/FEC Direct PHY Intel FPGA IP ka mokhoa oa DS?
A: Mokhoa oa DS o tšehetsoa feela bakeng sa liprothokholo tse boletsoeng tsa simplex eseng bakeng sa mekhoa e tloaelehileng ea TX/RX e nang le GTS PMA/FEC Direct PHY Intel FPGA IP, ntle le ha parameter ea melao ea tlhophiso ea PMA e behiloe ho SDI kapa HDMI.

Litokomane / Lisebelisoa

Intel E-Series 5 GTS Transceiver [pdf] Bukana ea Mosebelisi E-Series, D-Series, E-Series 5 GTS Transceiver, E-Series, 5 GTS Transceiver, GTS Transceiver, Transceiver

Litšupiso

• Bukana ea Mosebelisi