Intel 4G Turbo-V FPGA IP
Mabapi le 4G Turbo-V Intel® FPGA IP
Likhoutu tsa mecha ea tokiso ea Forward-Error (FEC) hangata li ntlafatsa ho sebetsa hantle ha matla a litsamaiso tsa puisano tse se nang mohala. Likhoutu tsa Turbo li loketse likhokahano tsa mehala tsa 3G le 4G (mohlala, ho UMTS le LTE) le likhokahano tsa satellite. U ka sebelisa likhoutu tsa Turbo lits'ebetsong tse ling tse hlokang phetisetso ea tlhaiso-leseling e tšepahalang ka li-bandwidth kapa lihokelo tsa likhokahano tse thibetsoeng ka lebaka la lerata le senyang data. 4G Turbo-V Intel® FPGA IP e na le accelerator e theolelang le uplink bakeng sa vRAN mme e kenyelletsa Turbo Intel FPGA IP. The downlink accelerator e eketsa redundancy ho data ka mokhoa oa boitsebiso bo lekanang.The uplink accelerator e sebelisa redundancy ho lokisa palo e utloahalang ea liphoso tsa mocha.
Lintlha Tse Amanang
- Turbo Intel FPGA IP User Guide
- 3GPP TS 36.212 mofuta 15.2.1 Hlakola 15
4G Turbo-V Intel FPGA IP Features
The downlink accelerator e kenyelletsa:
- Khoutu block cyclic redundancy code (CRC) attachment
- Turbo encoder
- Sebali sa sekhahla sa Turbo se nang le:
- Subblock interleaver
- 'Mokelli e nyenyane
- Sekhethi se senyenyane
- Ho pruner hanyane
Accelerator ea uplink e kenyelletsa:
- Subblock deinterleaver
- Turbo decoder e nang le cheke ea CRC
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
4G Turbo-V Intel FPGA IP Sesebelisoa sa Tšehetso ea Lelapa
Intel e fana ka maemo a latelang a ts'ehetso ea sesebelisoa bakeng sa Intel FPGA IP:
- Tšehetso e tsoetseng pele-IP e teng bakeng sa ho etsisa le ho bokelloa bakeng sa lelapa la sesebelisoa sena. Lenaneo la FPGA file (.pof) tšehetso ha e fumanehe bakeng sa software ea Beta ea Quartus Prime Pro Stratix 10 Edition 'me kahoo ho koala nako ea IP ho ke ke ha tiisetsoa. Mehlala ea nako e kenyelletsa likhakanyo tsa pele tsa boenjiniere tsa tieho e ipapisitseng le litaba tsa morao-rao tsa moralo. Mefuta ea nako e ka fetoha ha tlhahlobo ea silicon e ntlafatsa khokahano lipakeng tsa silicon ea 'nete le mefuta ea nako. U ka sebelisa setsi sena sa IP bakeng sa meralo ea sistimi le lithuto tsa tšebeliso ea lisebelisoa, papiso, pinout, tlhahlobo ea morao-rao ea sistimi, litekolo tsa nako ea mantlha (tekanyetso ea liphaephe), le leano la phetisetso ea I/O (bophara ba tsela ea data, botebo ba ho phatloha, maemo a I/O ).
- Tšehetso ea pele-Intel e netefatsa IP core ka mefuta ea pele ea nako bakeng sa lelapa lena la sesebelisoa. IP core e fihlela litlhoko tsohle tsa ts'ebetso, empa e kanna ea ba e ntse e hlahlojoa nako bakeng sa lelapa la sesebelisoa. U ka e sebelisa meralong ea tlhahiso ka hloko.
- Tšehetso ea ho qetela-Intel e netefatsa IP ka mefuta ea ho qetela ea nako bakeng sa lelapa lena la sesebelisoa. IP e kopana le litlhoko tsohle tse sebetsang le tsa nako bakeng sa lelapa la sesebelisoa. U ka e sebelisa meralong ea tlhahiso.
4G Turbo-V IP Sesebelisoa sa Tšehetso ea Lelapa
| Lelapa la Sesebelisoa | Tšehetso |
| Intel Agilex™ | Tsoela pele |
| Intel Arria® 10 | Qetellong |
| Intel Stratix® 10 | Tsoela pele |
| Malapa a lisebelisoa tse ling | Ha ho tšehetso |
Tlhahisoleseding ea Phatlalatso bakeng sa 4G Turbo-V Intel FPGA IP
Liphetolelo tsa Intel FPGA IP li tsamaisana le mefuta ea software ea Intel Quartus® Prime Design Suite ho fihlela v19.1. Ho qala ka Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP e na le leano le lecha la phetolelo. Nomoro ea Intel FPGA IP (XYZ) e ka fetoha ka mofuta o mong le o mong oa software ea Intel Quartus Prime. Phetoho ho:
- X e bontša phetoho e kholo ea IP. Haeba u nchafatsa software ea Intel Quartus Prime, u tlameha ho nchafatsa IP.
- Y e bonts'a IP e kenyelletsa likarolo tse ncha. Nchafatsa IP ea hau ho kenyelletsa likarolo tsena tse ncha.
- Z e bonts'a IP e kenyelletsa liphetoho tse nyane. Hlahisa IP ea hau bocha ho kenyelletsa liphetoho tsena.
4G Turbo-V Tlhahisoleseding ea Phallo ea IP
| Ntho | Tlhaloso |
| Phetolelo | 1.0.0 |
| Letsatsi la ho nšoa | Mmesa 2020 |
Ts'ebetso ea 4G Turbo-V le Tšebeliso ea Lisebelisoa
Intel e hlahisitse tšebeliso ea lisebelisoa le ts'ebetso ka ho bokella meralo ka Intel Quartus Prime software v19.1. Sebelisa feela liphetho tse hakanyetsoang bakeng sa khakanyo ea pele ea lisebelisoa tsa FPGA (mohlala, adaptive logic modules (ALMs)) tseo projeke e li hlokang. Lebelo la sepheo ke 300 MHz.
Ts'ebeliso ea Lisebelisoa tsa Downlink Accelerator le Maqhubu a Maholo a Maqhubu a Intel Arria 10 Devices
| Mojule | fMAX (MHz) | Li-ALM | ALUTs | Ngoliso | Mehopolo (Bits) | RAM Blocks (M20K) | DSP Blocks |
| Downlink accelerator | 325.63 | 9,373 | 13,485 | 14,095 | 297,472 | 68 | 8 |
| Khokahano ea CRC | 325.63 | 39 | 68 | 114 | 0 | 0 | 0 |
| Turbo encoder | 325.63 | 1,664 | 2,282 | 1154 | 16,384 | 16 | 0 |
| Reite matcher | 325.63 | 7,389 | 10,747 | 12,289 | 274,432 | 47 | 8 |
| Subblock interleaver | 325.63 | 2,779 | 3,753 | 5,559 | 52,416 | 27 | 0 |
| 'Mokelli e nyenyane | 325.63 | 825 | 1,393 | 2,611 | 118,464 | 13 | 4 |
| Sekhethi se senyenyane le se pruner | 325.63 | 3,784 | 5,601 | 4,119 | 103,552 | 7 | 4 |
Tšebeliso ea Lisebelisoa tsa Uplink Accelerator le Maqhubu a Maholo a Matla a Intel Arria 10 Devices
| Mojule | fMAX (MHz) | Li-ALM | Ngoliso | Mehopolo (Bits) | RAM Blocks (M20K) | DSP Blocks |
| Uplink accelerator | 314.76 | 29480 | 30,280 | 868,608 | 71 | 0 |
| Subblock deinterleaver | 314.76 | 253 | 830 | 402,304 | 27 | 0 |
| Turbo decoder | 314.76 | 29,044 | 29,242 | 466,304 | 44 | 0 |
Ho rala ka 4G Turbo-V Intel FPGA IP
4G Turbo-V IP Directory Sebopeho
U tlameha ho kenya IP ka letsoho ho tsoa ho setsi sa IP.
Sebopeho sa Directory ea ho Kenya
Ho hlahisa 4G Turbo-V IP
O ka hlahisa downlink kapa uplink accelerator. Bakeng sa accelerator ea uplink, nkela dl sebaka ka ul bukeng kapa file mabitso.
- Bula software ea Intel Quartus Prime Pro.
- Khetha File ➤ Setsebi se Secha sa Morero.
- Tobetsa E latelang.
- Kenya lebitso la morero dl_fec_wrapper_top 'me u kenye sebaka sa morero.
- Khetha sesebelisoa sa Arria 10.
- Tobetsa Qetella.
- Bula faele ea dl_fec_wrapper_top.qpf file e fumaneha bukeng ea morero Ho hlaha wizate ea morero.
- Ho thebo ea Moqapi oa Platform:
- Theha faele ea dl_fec_wrapper_top.ip file ho sebelisa hardware tcl file.
- Tobetsa Hlahisa HDL ho hlahisa moralo files.
- Ho Thepa ea Hlahisa, tobetsa Hlahisa tsamaiso ea benche ea liteko.
- Tobetsa Eketsa Tsohle ho eketsa motsoako files ho morero. The files li ho src\ip\dl_fec_wrapper_top\dl_fec_wrapper_10\synth.
- Seta dl_fec_wrapper_top.v file joalo ka setsi sa boemo bo holimo.
- Tobetsa Start Compilation ho hlophisa morero ona.
Ho etsisa 4G Turbo-V IP
Mosebetsi ona ke oa ho etsisa accelerator ea downlink. Ho etsisa accelerator ea uplink nka sebaka sa dl ka ul bukeng ka 'ngoe kapa file lebitso.
- Bula simulator ea ModelSim 10.6d FPGA Edition.
- Fetola bukana ho src\ip\dl_fec_wrapper_top_tb \dl_fec_wrapper_top_tb\sim\mentor
- Fetola QUARTUS_INSTALL_DIR bukeng ea hau ea Intel Quartus Prime ho msim_setup.tcl file, e leng ho \ sim\ mentor directory
- Kenya taelo etsa load_sim.tcl fensetereng ea transcript. Taelo ena e hlahisa laebrari files le ho bokella le ho etsisa mohlodi files ho msim_setup.tcl file. Li-vector tsa liteko li kene filename_update.sv ho \ sim directory.
The filentlafatso ea lebitso File Sebopeho
- Vector ea teko e tsamaellanang files li ho sim\mentor\test_vectors
- Log.txt e na le sephetho sa lipakete tsohle tsa liteko.
- Bakeng sa sehokelo sa theolelo, encoder_pass_file.txt e na le tlaleho ea pasa ea index e 'ngoe le e 'ngoe ea lipakete tsa liteko le encoder_file_error.txt e na le tlaleho e hlolehileng ea index e 'ngoe le e 'ngoe ea lipakete tsa liteko.
- Bakeng sa accelerator ea uplink, Error_file.txt e na le tlaleho e hlolehileng ea index e 'ngoe le e 'ngoe ea lipakete tsa liteko.
4G Turbo-V Intel FPGA IP Tlhaloso ea Mosebetsi
4G Turbo-V Intel FPGA IP e na le accelerator ea downlink le accelerator ea uplink.
- 4G Turbo-V Architecture leqepheng la 9
- 4G Turbo-V Lipontšo le Litšebelisano leqepheng la 11
- Litšoantšo tsa Nako tsa 4G Turbo-V leqepheng la 15
- 4G Turbo-V Latency le Phello leqepheng la 18
4G Turbo-V Architecture
4G Turbo-V Intel FPGA IP e na le accelerator ea downlink le accelerator ea uplink.
4G Downlink Accelerator
4G Turbo downlink accelerator e na le "code block attachment block" ea CRC le encoder ea Turbo (Intel Turbo FPGA IP) le tekanyo ea litekanyetso. Lintlha tse kentsoeng li bophara ba 8-bit mme data e hlahisoang e bophara ba 24-bit. Sekhahla sa sekhahla se na le li-interleavers tse tharo tsa li-subblock, khetho e nyane, le pokello e nyane.
The 4G downlink accelerator e sebelisa khoutu thibela CRC attachment le 8-bit parallel CRC computation algorithm. Kenyelletso ho block attachment ea CRC e bophara ba 8-bit. Ka mokhoa o tloaelehileng, palo ea lisebelisoa ho thibela CRC ke k-24, moo k e leng boholo ba thibela e thehiloeng ho index ea boholo. Tatelano e eketsehileng ea CRC ea li-bits tse 24 e khomaretsoe ho "code block" e kenang ea data ka har'a "CRC attachment block" ebe e fetela ho encoder ea Turbo. Ka mokhoa oa CRC bypass, palo ea lintho tse kentsoeng ke k ea boholo ba 8-bit e fetiselitsoeng ho "encoder block" ea Turbo.
Turbo encoder e sebelisa khoutu ea convolutional e bapileng. Convolutional encoder e khouto tatelano ea tlhahisoleseling mme e 'ngoe ea khouto e khouto e khouto mofuta o fapaneng oa tatelano ea tlhahisoleseling. Turbo encoder e na le li-encoder tse peli tsa convolutional state 8 le interleaver e le 'ngoe ea khoutu ea Turbo. Bakeng sa tlhaiso-leseling e batsi mabapi le encoder ea Turbo, sheba ho Turbo IP Core User Guide. Sekhahla sa sekhahla se tsamaisana le palo ea li-bits tse thibelang lipalangoang ho palo ea li-bits tseo IP e li fetisang kabong eo. Kenyelletso le tlhahiso ea sekhahla sa sekhahla ke li-bits tse 24. IP e hlalosa tekanyo e lekanang bakeng sa liteishene tsa lipalangoang tse nang le khoutu ea Turbo bakeng sa block e 'ngoe le e 'ngoe ea khoutu. Sekhahla sa sekhahla se kenyelletsa: subblock interleaver, bit collector le bit selector. The downlink accelerator e theha "subblock" e kentsoeng bakeng sa phallo e 'ngoe le e' ngoe e tsoang ho Turbo coding. Melatsoana e kenyelletsa molaetsa oa bit stream, 1st parity bit stream le 2nd parity bit stream. Kenyelletso le tlhahiso ea subblock interleaved ke li-bits tse 24 ka bophara. Mokokelli o kopanya melapo e tsoang ho subblock interleaver. Sebaka sena se na le li-buffer tse bolokang:
- Melaetsa le li-filler tse nolofalletsang likotoana ho tsoa ho block block li tsamaile.
- Subblock e kenyellelitse li-parity bits le likotoana tsa tsona tse fapaneng.
Bit Collector
4G Channel Uplink Accelerator
4G Turbo uplink accelerator e na le subblock deinterleaver le turbo decoder (Intel Turbo FPGA IP).
Deinterleaver e na le li-blocks tse tharo tseo ho tsona li-blocks tse peli tsa pele li nang le symmetrical le boloko ba boraro bo fapaneng.
Latency ea lets'oao le itokisitseng ke 0.
Deinterleaver
Haeba o bulela mokhoa oa ho pota-pota bakeng sa subblock deinterleaver, IP e bala data ha e ntse e ngola lintlha tsa memori ea memori libakeng tse latellanang. IP e bala data le ha e ngola data ntle le ho kena-kenana. Palo ea data e kentsoeng ho subblock deinterleaver ke K_π ka mokhoa oa bypass mme bolelele ba data e hlahisoang ke k boholo (k ke boholo ba block block bo ipapisitseng le boleng ba cb_size_index). Ho lieha ha data ea tlhahiso ea subblock deinterleaver ho itšetlehile ka boholo ba block block K_π. IP e bala lintlha feela ka mor'a hore u ngole boholo ba K_π khoutu ea data e kentsoeng. Ka hona, nako ea sephetho e boetse e kenyelletsa nako ea ho ngola. The latency ho subblock interleaver data output ke K_π+17. Turbo decoder e bala tatellano e ka fetisoang haholo, e ipapisitse le sampe seng hore e amohele. Bakeng sa tlhaloso e qaqileng, sheba Turbo Core IP User Guide. Ho khetholla liphoso tsa ho lokisa likhoutu ke papiso ea menyetla ea likhoutu tse fapaneng tsa convolutional. Turbo decoder e na le li-decoder tse peli tsa soft-in soft-out (SISO), tse sebetsang khafetsa. Sehlahisoa sa pele (dekhoutara e ka holimo) se fepa ea bobeli ho theha "Turbo decoding iteration". Interleaver le deinterleaver li thibela ho hlophisa data hape ts'ebetsong ena.
Lintlha Tse Amanang
Tataiso ea mosebelisi ea Turbo IP Core
4G Turbo-V Lipontšo le Litšebelisano
Downlink Accelerator
Lipontšo tsa Downlink Accelerator
| Lebitso la Letshwao | Tataiso | Bit Width | Tlhaloso |
| clk | Kenyeletso | 1 | 300 MHz ho kenya oache. Lipontšo tsohle tsa Turbo-V IP interface li lumellana le oache ena. |
| reset_n | Kenyeletso | 1 | E hlophisa bocha mohopolo oa kahare oa IP kaofela. |
| sink_a sebetsa | Kenyeletso | 1 | E hlahisoa ha data e sink_data e sebetsa. Ha sink_valid e sa boleloa, IP strops e sebetsa ho fihlela sink_valid e tiisitsoe hape. |
| sink_data | Kenyeletso | 8 | Ka tloaelo e jara bongata ba litaba tse fetisitsoeng. |
| sink_sop | Kenyeletso | 1 | E bontša ho qala ha pakete e kenang |
| sink_eop | Kenyeletso | 1 | E supa pheletso ea pakete e kenang |
| sink_ready | Sephetho | 1 | E bontša hore na IP e ka amohela data neng |
| Sink_phoso | Kenyeletso | 2 | Mask oa li-bit tse peli ho bonts'a liphoso tse amang data e fetiselitsoeng potolohong ea hajoale. |
| Crc_ nolofalletsa | Kenyeletso | 1 | E nolofalletsa boloko ba CRC |
| Cb_size_index | Kenyeletso | 8 | Saese ya boloko ba khoutu ya ho kenya K |
| sink_rm_out_size | Kenyeletso | 20 | Rata boholo ba block output ea matcher, e tsamaellanang le E. |
| sink_code_blocks | Kenyeletso | 15 | Saese e bonolo ea buffer bakeng sa boloko ba khoutu ea hajoale Ncb |
| sink_rv_idx | Kenyeletso | 2 | Lenane la tlhahiso ea ho hloka mosebetsi (0,1,2 kapa 3) |
| sink_rm_bypass | Kenyeletso | 1 | E nolofalletsa mokhoa oa ho pota-pota ka tekanyo ea tekanyo |
| sink_filler_bits | Kenyeletso | 6 | Palo ea li-filler e kenyelletsa IP e kentsoeng ho transmitter ha IP e etsa karohano ea li-code block. |
| mohloli_o sebetsa | Sephetho | 1 | E tiisitsoe ke IP ha ho na le data e nepahetseng e lokelang ho hlahisoa. |
| e tsoela pele… | |||
| Lebitso la Letshwao | Tataiso | Bit Width | Tlhaloso |
| data_mohloli | Sephetho | 24 | E jara boholo ba lintlha tse fetisitsoeng. Lintlha tsena li fumaneha moo ho netefalitsoeng hore li nepahetse. |
| mohloli_sop | Sephetho | 1 | E supa qalo ea pakete. |
| mohloli_eop | Sephetho | 1 | E supa pheletso ea pakete. |
| source_ready | Kenyeletso | 1 | Kamohelo ea data e nepahetse moo lets'oao le itokiselitseng le tiisitsoeng. |
| phoso_ea_mohloli | Sephetho | 2 | Letšoao la phoso le phatlalalitsoe ho tsoa ho Turbo Encoder e bonts'ang tlolo ea molao ea Avalon-ST lehlakoreng la mohloli
• 00: Ha ho phoso • 01: Qalo ea pakete e sieo • 10: Karolo e sieo ea pakete • 11: Qetello e sa lebelloang ea pakete Mefuta e meng ea liphoso le eona e ka tšoauoa e le 11. |
| Mohloli_blk_size | Sephetho | 13 | Saese ya boloko ba khoutu ya tlhahiso K |
Li-interface tsa Uplink Accelerator
Lipontšo tsa Uplink Accelerator
| Letshwao | Tataiso | Bit Width | Tlhaloso |
| clk | Kenyeletso | 1 | 300 MHz ho kenya oache. Lipontšo tsohle tsa Turbo-V IP interface li lumellana le oache ena. |
| reset_n | Kenyeletso | 1 | Ho seta bocha lets'oao la oache ea ho kenya |
| sink_a sebetsa | Kenyeletso | 1 | Keletso ea Avalon e nepahetse |
| sink_data | Kenyeletso | 24 | Lintlha tse kentsoeng ka Avalon |
| sink_sop | Kenyeletso | 1 | Ho qala ha pakete ea Avalon streaming |
| sink_eop | Kenyeletso | 1 | Qetellong ea sephutheloana sa Avalon |
| e tsoela pele… | |||
| Letshwao | Tataiso | Bit Width | Tlhaloso |
| sink_ready | Kenyeletso | 1 | Kenyelletso ea Avalon e se e loketse |
| conf_valid | Kenyeletso | 1 | Kopo ea litlhophiso e nepahetse |
| cb_size_index | Kenyeletso | 8 | Thibela boholo bo pheta-phetoang index |
| max_iteration | Kenyeletso | 5 | Phetolelo e kholo |
| rm_bypass | Kenyeletso | 1 | E nolofalletsa mokhoa oa bypass |
| rekisa_CRC24A | Kenyeletso | 1 | E totobatsa mofuta oa CRC oo u o hlokang bakeng sa block ea hajoale ea data:
• 0: CRC24A • 1: CRC24B |
| conf_ready | Kenyeletso | 1 | Kopo ea tlhophiso e se e loketse |
| mohloli_o sebetsa | Sephetho | 1 | Sephetho sa Avalon se nepahetse |
| data_mohloli | Sephetho | 16 | Lintlha tse hlahisoang ke Avalon |
| mohloli_sop | Sephetho | 1 | Phakete ea Avalon e qala pakete |
| mohloli_eop | Sephetho | 1 | Qetellong ea pakete ea Avalon phallela |
| phoso_ea_mohloli | Sephetho | 2 | Letšoao la phoso le bonts'ang litlolo tsa protocol tsa Avalon ka lehlakoreng la mohloli:
• 00: Ha ho phoso • 01: Qalo ea pakete e sieo • 10: Karolo e sieo ea pakete • 11: Qetello e sa lebelloang ea pakete Mefuta e meng ea liphoso le eona e ka tšoauoa e le 11. |
| source_ready | Sephetho | 1 | Phalliso ea Avalon e se e loketse |
| CRC_mofuta | Sephetho | 1 | E bonts'a mofuta oa CRC o neng o sebelisetsoa block block ea hajoale:
• 0: CRC24A • 1: CRC24B |
| mohloli_blk_size | Sephetho | 13 | E hlalosa boholo ba boloko bo tswang |
| CRC_feta | Sephetho | 1 | E bontša hore na CRC e atlehile:
• 0: Ho hloleha • 1: Feta |
| mohloli_iter | Sephetho | 5 | E bonts'a palo ea makhetlo a halofo ka mor'a moo decoder ea Turbo e emisang ho sebetsa block block ea hajoale. |
Avalon Streaming Interfaces ho DSP Intel FPGA IP
Li-interfaces tsa Avalon li hlalosa protocol e tloaelehileng, e feto-fetohang le e tloaelehileng bakeng sa phetisetso ea data ho tloha mohloling oa mohloli ho ea ho sink interface. Sebopeho sa ho kenya letsoho ke teba ea Avalon ea ho phallela 'me sebopeho sa tlhahiso ke mohloli oa ho phallela oa Avalon. Sebopeho sa phallo ea Avalon se ts'ehetsa phetisetso ea lipakete ka lipakete tse hokahaneng liteisheneng tse ngata. Lipontšo tsa sehokelo sa Avalon li ka hlalosa li-interfaces tsa setso tse tšehetsang data e le 'ngoe ntle le tsebo ea liteishene kapa meeli ea lipakete. Likhokahano tse joalo hangata li na le lintlha, tse itokisitseng, le matšoao a nepahetseng. Li-interface tsa Avalon le tsona li ka ts'ehetsa liprothokholo tse rarahaneng bakeng sa phetisetso ea ho phatloha le ho fetisoa ka lipakete ka lipakete tse hokahaneng liteisheneng tse ngata. Sehokelo sa phallo ea Avalon ka tlhaho se hokahanya meralo ea li-multichannel, e u lumellang ho fihlela ts'ebetsong e sebetsang hantle, e nang le nako e ngata ntle le ho kenya ts'ebetsong mohopolo o rarahaneng oa taolo. Li-interfaces tsa Avalon li tšehetsa khatello ea morao-rao, e leng mokhoa oa ho laola phallo moo sink e ka bontšang mohloli ho emisa ho romela data. Sink hangata e sebelisa khatello ea morao-rao ho emisa phallo ea data ha li-buffers tsa FIFO li tletse kapa ha e na le tšubuhlellano ho tlhahiso ea eona.
Lintlha Tse Amanang
Litlhaloso tsa Avalon Interface
4G Turbo-V Litšoantšo tsa Nako
Setšoantšo sa Nako bakeng sa ho Ngola Logic ka Codeblock 40
IP:
- E beha li-bits tse 20 lefeela kholomong ea 0 ho isa ho ea 19 'me e ngola lintlha tsa data ho tloha kholomong ea 20.
- E ngola likotoana tsohle tse 44 mohopolong ka li-clock tse 6.
- E ngola likotoana tsa pheliso ea trellis kholomong ea 28 ho isa ho ea 31.
- Keketso ngola aterese bakeng sa mola o mong le o mong.
- E hlahisa lets'oao le lumellang ho ngola bakeng sa RAM e le 'ngoe ea 8 ka nako.
IP ha e ngole li-filler bits ho RAM. Sebakeng seo, IP e siea sets'oants'o sa sebaka bakeng sa li-filter bits ho RAM ebe e kenya likotoana tsa NULL ho tlhahiso nakong ea ts'ebetso ea ho bala. Mongolo oa pele o qala kholomong ea 20.
Sets'oants'o sa Nako bakeng sa Ho Bala Monahano ka Codeblock 40
Bakeng sa 'malo o mong le o mong, u bona li-bits tse 8 ka nako e le' ngoe ea oache empa ho na le likotoana tse peli feela tse sebetsang. IP e ngola likotoana tsena tse peli ho rejistara ea shift. Ha IP e etsa li-bits tse 8 e li romella ho sebopeho sa tlhahiso.
Setšoantšo sa Nako bakeng sa ho Ngola Logic ka Codeblock 6144
Li-filler bits li tsoa kholomong ea 0 ho isa ho 27 'me lintlha tsa data li tsoa kholomong ea 28. IP:
- E ngola likotoana tsohle tse 6,148 mohopolong ka li-clock tse 769.
- E ngola likotoana tsa pheliso ea trellis kholomong ea 28 ho isa ho ea 31.
- Keketso ngola aterese bakeng sa mola o mong le o mong.
- E hlahisa lets'oao la ho ngola le etselitsoeng 8 RAM ka nako.
IP ha e ngole li-filler bits ho RAM. Sebakeng seo IP e siea sets'oants'o sa sebaka bakeng sa li-filter bits ho RAM ebe e kenya likotoana tsa NULL tlhahiso nakong ea ts'ebetso ea ho bala. Mongolo oa pele o qala kholomong ea 28.
Sets'oants'o sa Nako bakeng sa Ho Bala Monahano ka Codeblock 6144
Lehlakoreng le baloang, ho bala ka 'ngoe ho fana ka likotoana tse 8. Ha u ntse u bala mola oa 193, IP e bala li-bits tse 8, empa ho na le karolo e le 'ngoe feela e sebetsang. IP e etsa li-bits tse robeli tse nang le li-shift register ebe e li romela ka ho bala ho tloha kholomong e latelang.
Kena Letšoao la Nako
Sets'oants'o sa Nako ea Sephetho
4G Turbo-V Latency le throughput
The latency e lekanngoa pakeng tsa ho kenya pakete ea pele ea SOP ho hlahisa pakete ea pele ea SOP. Nako ea ts'ebetso e lekantsoe lipakeng tsa sephutheloana sa pele sa SOP ho hlahisa pakete ea ho qetela ea EOP.
Downlink accelerator
Phallo ke sekhahla seo IP e ka pompang se kenang ka har'a accelerator ea downlink ha e se e loketse.
Downlink Accelerator Latency, Nako ea Ts'ebetso, le Phallo
Ka boholo ba K ea 6,144 le E boholo ba 11,522. Nako ea ts'ebetso e lekantsoeng bakeng sa li-code tse 13. Lebelo la oache ke 300 MHz.
| K | E | Ho lieha ho fihla | Nako ea ho sebetsa | Kenyelletso | ||
| (lipotoloho) | (rona) | (lipotoloho) | (rona) | (%) | ||
| 6,144 | 11,552 | 3,550 | 11.8 | 14,439 | 48.13 | 95 |
Palo ea nako ea ho lieha le ho sebetsa
- Palo e bonts'a mokhoa oa ho bala latency, nako ea ts'ebetso, le ho feta.
K Size khahlano le Latency
K Size khahlano le Latency
- k=40 ho isa ho 1408
Uplink Accelerator Latency le Processing Nako
- Ka palo e kholo ea ho pheta-pheta = 6. Lebelo la oache ke 300 MHz.
K E Ho lieha ho fihla Nako ea ho sebetsa (lipotoloho) (rona) (lipotoloho) (rona) 86 40 316 1.05 318 1.06 34,560 720 2,106 7.02 2,150 7.16 34,560 1,408 3,802 12.67 3,889 12.96 34,560 1,824 4,822 16.07 4,935 16.45 28,788 2,816 7,226 24.08 7,401 24.67 23,742 3,520 8,946 29.82 9,165 30.55 34,560 4,032 10,194 33.98 10,445 34.81 26,794 4,608 11,594 38.64 11,881 39.60 6,480 5,504 13,786 45.95 14,129 47.09 12,248 6,144 15,338 51.12 15,721 52.40
Uplink Accelerator Latency le Processing Nako
- Ka palo e kholo ea ho pheta-pheta = 8
| K | E | Ho lieha ho fihla | Nako ea ho sebetsa | ||
| (lipotoloho) | (rona) | (lipotoloho) | (rona) | ||
| 86 | 40 | 366 | 1.22 | 368 | 1.22 |
| 34,560 | 720 | 2,290 | 7.63 | 2,334 | 7.78 |
| 34,560 | 1,408 | 4,072 | 13.57 | 4,159 | 13.86 |
| 34,560 | 1,824 | 5,144 | 17.14 | 5,257 | 17.52 |
| 28,788 | 2,816 | 7,672 | 25.57 | 7,847 | 26.15 |
| e tsoela pele… | |||||
| 23,742 | 3,520 | 9,480 | 31.6 | 9,699 | 32.33 |
| 34,560 | 4,032 | 10,792 | 35.97 | 11,043 | 36.81 |
| 26,794 | 4,608 | 12,264 | 40.88 | 12,551 | 41.83 |
| 6,480 | 5,504 | 14,568 | 48.56 | 14,911 | 49.70 |
| 12,248 | 6,144 | 16,200 | 54 | 16,583 | 55.27 |
K Size vs Latency
- Bakeng sa max_iter=6
Setšoantšo sa 19. K Size vs Processing Time
- Bakeng sa max_iter=6
K Size vs Latency
- Bakeng sa max_iter=8
K Size vs Nako ea Ts'ebetso
- Bakeng sa max_iter=8
Nalane ea Tokomane ea Tokomane ea 4G Turbo-V Intel FPGA IP User Guide
| Letsatsi | IP Version | Intel Quartus Prime Software Version | Liphetoho |
| 2020.11.18 | 1.0.0 | 20.1 | Tafole e tlositsoeng ka hare Ts'ebetso ea 4G Turbo-V le Tšebeliso ea Lisebelisoa |
| 2020.06.02 | 1.0.0 | 20.1 | Tokollo ea pele. |
Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
Litokomane / Lisebelisoa
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Intel 4G Turbo-V FPGA IP [pdf] Bukana ea Mosebelisi 4G Turbo-V FPGA IP, 4G Turbo-V, FPGA IP |
