25G Ethernet Intel® FPGA IP Release Notes
Bukana ea Mosebelisi
25G Ethernet Intel FPGA IP Release Notes (Intel Agilex Devices)
Liphetolelo tsa Intel® FPGA IP li tsamaisana le mefuta ea software ea Intel Quartus® Prime Design Suite ho fihlela v19.1. Ho qala ka Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP e na le leano le lecha la phetolelo.
Nomoro ea Intel FPGA IP (XYZ) e ka fetoha ka mofuta o mong le o mong oa software ea Intel Quartus Prime. Phetoho ho:
- X e bontša phetoho e kholo ea IP. Haeba u nchafatsa software ea Intel Quartus Prime, u tlameha ho nchafatsa IP.
- Y e bonts'a IP e kenyelletsa likarolo tse ncha. Nchafatsa IP ea hau ho kenyelletsa likarolo tsena tse ncha.
- Z e bonts'a IP e kenyelletsa liphetoho tse nyane. Hlahisa IP ea hau bocha ho kenyelletsa liphetoho tsena.
1.1. 25G Ethernet Intel FPGA IP v1.0.0
Lethathamo la 1. v1.0.0 2022.09.26
| Intel Quartus Prime Version | Tlhaloso | Tšusumetso |
| 22.3 | Ts'ehetso e ekelitsoeng bakeng sa lelapa la sesebelisoa sa Intel Agilex™ F-tile. • Ke lebelo la lebelo la 25G feela le tšehetsoeng. • 1588 Precision Time Protocol ha e tšehetsoe. |
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Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
ISO
9001:2015
Ngodisitsoe
25G Ethernet Intel FPGA IP Release Notes (Intel Stratix 10 Devices)
Haeba lengolo la tokollo le le sieo bakeng sa mofuta o itseng oa IP, IP ha e na liphetoho ho mofuta oo. Bakeng sa tlhaiso-leseling ka lintlafatso tsa IP ho fihla ho v18.1, sheba Lintlha tsa Phatlalatso tsa Intel Quartus Prime Design Suite.
Liphetolelo tsa Intel FPGA IP li tsamaisana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihlela v19.1. Ho qala ka Intel Quartus Prime Design Suite software version 19.2, Intel
FPGA IP e na le leano le lecha la ho fetolela.
Nomoro ea Intel FPGA IP (XYZ) e ka fetoha ka mofuta o mong le o mong oa software ea Intel Quartus Prime. Phetoho ho:
- X e bontša phetoho e kholo ea IP. Haeba u nchafatsa software ea Intel Quartus Prime, u tlameha ho nchafatsa IP.
- Y e bonts'a IP e kenyelletsa likarolo tse ncha. Nchafatsa IP ea hau ho kenyelletsa likarolo tsena tse ncha.
- Z e bonts'a IP e kenyelletsa liphetoho tse nyane. Hlahisa IP ea hau bocha ho kenyelletsa liphetoho tsena.
Lintlha Tse Amanang
- Lintlha tsa Phatlalatso ea Phatlalatso ea Intel Quartus Prime Design Suite
- 25G Ethernet Intel Stratix®10 FPGA IP User Guide Archives
- 25G Ethernet Intel Stratix® 10 FPGA IP Design Example User Guide Archives
- Errata bakeng sa 25G Ethernet Intel FPGA IP Sebakeng sa Tsebo
2.1. 25G Ethernet Intel FPGA IP v19.4.1
Lethathamo la 2. v19.4.1 2020.12.14
| Intel Quartus Prime Version | Tlhaloso | Tšusumetso |
| 20.4 | Ntlafatso ea ho lekola bolelele ho liforeimi tsa VLAN: • Liphetolelong tse fetileng tsa 25G Ethernet Intel FPGA IP, phoso e feteletseng ea foreimi e boleloa ha maemo a latelang a finyelloa: 1. VLAN a. Ho fumanwa ha VLAN ho butswe. b. IP e fetisa/e amohela liforeimi tse bolelele bo fihlang ho bolelele ba foreimi ea TX/RX mmoho le 1 ho isa ho 4 octet. 2. SVLAN a. Ho fumanwa ha SVLAN ho butswe. b. IP e fetisa/e amohela liforeimi tse bolelele bo fihlang ho bolelele ba foreimi ea TX/RX mmoho le 1 ho isa ho 8 octet. • Besheneng ena, IP e nchafalitsoe ho lokisa boitšoaro bona. |
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| E ntlafalitse mokhoa oa ho fihlella oa Avalon® oa 'mapa oa memori ho boemo ba_* ho thibela nako ea nako ea mohopolo oa Avalon nakong ea ho balloa liaterese tse sieo: • Liphetolelong tse fetileng tsa 25G Ethernet Intel FPGA IP, Avalon memory-mapped interface e balla liaterese tse seng teng ho status_* interface e ne e tla tiisa status_waitrequest ho fihlela kopo ea Avalon memorymapped master e fela. Taba ena e se e lokisitsoe hore e se ke ea ts'oara kopo ha aterese e seng teng e fumaneha. |
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| Mefuta e fapaneng ea RS-FEC e se e tšehetsa tlhahiso ea 100%. | — |
2.2. 25G Ethernet Intel FPGA IP v19.4.0
Lethathamo la 3. v19.4.0 2019.12.16
| Intel Quartus Prime Version | Tlhaloso | Tšusumetso |
| 19.4 | rx_am_lock phetoho ea boitšoaro: • Liphetolelong tse fetileng tsa 25G Ethernet Intel FPGA IP, lets'oao la rx_am_lock le sebetsa ka mokhoa o ts'oanang le rx_block_lock ho mefuta eohle. • Phetolelong ena, bakeng sa mefuta e fapaneng ea RSFEC e lumelletsoeng ea IP, rx_am_lock joale e bolela ha ho notlelloa ha tokiso ho fihletsoe. Bakeng sa mefuta e sa lumelleng ea RSFEC, rx_am_lock e ntse e sebetsa ka mokhoa o ts'oanang le rx_block_lock. |
Letšoao la sehokelo, rx_am_lock, le sebetsa ka tsela e fapaneng le liphetolelo tse fetileng bakeng sa mefuta e lumelletsoeng ea RSFEC. |
| E ntlafalitse Qalo ea Pakete ea RX MAC: • Liphetolelong tse fetileng, RX MAC e sheba feela litlhaku tsa START ho tseba ho qala ha pakete. • Phetolelong ena, RX MAC joale e hlahloba lipakete tse kenang bakeng sa Start of Frame Delimiter (SFD), ho phaella ho START tlhaku ka ho feletseng. • Haeba selelekela sa "pass-through mode" se butswe, MAC e sheba feela hore na ho na le litlhaku tse QALANG ho lumella selelekela sa tloaelo. |
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| E kentse rejisetara e ncha ho thusa ho hlahloba selelekela: • Lirejiseteng tsa RX MAC, rejisetara e ho offset 0x50A [4] e ka ngolloa ho 1 ho nolofalletsa ho hlahloba selelekela. Rejisetara ena ke "ha o tsotelle" ha selelekela sa ho feta se buletsoe. |
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2.3. 25G Ethernet Intel FPGA IP v19.3.0
Lethathamo la 4. v19.3.0 2019.09.30
| Intel Quartus Prime Version | Tlhaloso | Tšusumetso |
| 19.3 | Bakeng sa mofuta oa MAC+PCS+PMA, lebitso la mojule oa transceiver wrapper le se le hlahisoa ka matla. Sena se thibela ho thulana ha module ho sa batleheng haeba maemo a mangata a IP a sebelisoa tsamaisong. | — |
2.4. 25G Ethernet Intel FPGA IP v19.2.0
Lethathamo la 5. v19.2.0 2019.07.01
| Intel Quartus Prime Version | Tlhaloso | Tšusumetso |
| 19.2 | Moqapi Example bakeng sa 25G Ethernet Intel FPGA IP: • E ntlafalitse khetho ea khiti ea ntlafatso bakeng sa lisebelisoa tsa Intel Stratix® 10 ho tloha Intel Stratix 10 L-Tile GX Transceiver Signal Integrity Development Kit ho ea ho Intel Stratix 10 10 GX Signal Integrity L-Tile (Production) Ntlafatso Kit. |
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2.5. 25G Ethernet Intel FPGA IP v19.1
Lethathamo la 6. v19.1 Mmesa 2019
| Tlhaloso | Tšusumetso |
| E kentse tšobotsi e ncha-Mokhoa oa Adaptive bakeng sa Adaptation ea RX PMA: • E kentse paramethara e ncha—Lumella mokhoa oa ho ikamahanya le maemo a iketsang bakeng sa mokhoa oa RX PMA CTLE/DFE. |
Liphetoho tsena ke tsa boikhethelo. Haeba u sa ntlafatse IP ea hau ea mantlha, ha e na tšobotsi ena e ncha. |
| E reha lebitso bocha paramethara ea Enable Altera Debug Master Endpoint (ADME) ho nolofalletsa Native PHY Debug Master Endpoint (NPDME) joalo ka ha Intel e fetolela bocha software ea Intel Quartus Prime Pro Edition. Software ea Intel Quartus Prime Standard Edition e ntse e sebelisa Enable Altera Debug Master Endpoint (ADME). | — |
2.6. 25G Ethernet Intel FPGA IP v18.1
Lethathamo la 7. Version 18.1 September 2018
| Tlhaloso | Tšusumetso |
| E kentse tšobotsi e ncha-PMA ea Khetho: • E kentse paramethara e ncha—Core Variants. |
Liphetoho tsena ke tsa boikhethelo. Haeba u sa ntlafatse IP ea hau ea mantlha, ha e na likarolo tsena tse ncha. |
| • E kentse lets'oao le lecha bakeng sa 1588 Precision Time Protocol Interface—latency_sclk. | |
| Moqapi Example bakeng sa 25G Ethernet Intel FPGA IP: E reha bocha khetho ea lisebelisoa tsa ntlafatso bakeng sa lisebelisoa tsa Intel Stratix 10 ho tloha Stratix 10 GX FPGA Development Kit ho ea Stratix 10 L-Tile GX Transceiver Signal Integrity Development Kit. |
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Lintlha Tse Amanang
- 25G Ethernet Intel Stratix 10 FPGA IP User Guide
- 25G Ethernet Intel Stratix 10 FPGA IP Design Example Bukana ea Mosebelisi
- Errata bakeng sa 25G Ethernet IP core ho Tsebo Base
2.7. 25G Ethernet Intel FPGA IP v18.0
Lethathamo la 8. Version 18.0 May 2018
| Tlhaloso | Tšusumetso |
| Tokollo ea pele ea lisebelisoa tsa Intel Stratix 10. | — |
2.8. 25G Ethernet Intel Stratix 10 FPGA IP User Guide Archives
Liphetolelo tsa IP li tšoana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihla ho v19.1. Ho tsoa ho Intel Quartus Prime Design Suite software version 19.2 kapa hamorao, li-cores tsa IP li na le morero o mocha oa phetolelo ea IP.
Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.
| Intel Quartus Prime Version | IP Core Version | Bukana ea Mosebelisi |
| 20.3 | 19.4.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 20.1 | 19.4.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 19.4 | 19.4.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 19.3 | 19.3.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 19.2 | 19.2.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 19.1 | 19.1 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 18.1 | 18.1 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 18.0 | 18.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
2.9. 25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives
Liphetolelo tsa IP li tšoana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihla ho v19.1. Ho tsoa ho Intel Quartus Prime Design Suite software version 19.2 kapa hamorao, li-cores tsa IP li na le morero o mocha oa phetolelo ea IP.
Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.
| Intel Quartus Prime Version | IP Core Version | Bukana ea Mosebelisi |
| 19.1 | 19.1 | 25G Ethernet Intel Stratix 10 FPGA IP Design Example Bukana ea Mosebelisi |
| 18.1 | 18.1 | 25G Ethernet Intel Stratix 10 FPGA IP Design Example Bukana ea Mosebelisi |
| 18.0 | 18.0 | 25G Ethernet Intel Stratix 10 FPGA IP Design Example Bukana ea Mosebelisi |
25G Ethernet Intel FPGA IP Release Notes (Intel Arria 10 Devices)
Haeba lengolo la tokollo le le sieo bakeng sa mofuta o itseng oa IP, IP ha e na liphetoho ho mofuta oo. Bakeng sa tlhaiso-leseling ka lintlafatso tsa IP ho fihla ho v18.1, sheba Lintlha tsa Phatlalatso tsa Intel Quartus Prime Design Suite.
Liphetolelo tsa Intel FPGA IP li tsamaisana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihlela v19.1. Ho qala ka Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP e na le leano le lecha la phetolelo.
Nomoro ea Intel FPGA IP (XYZ) e ka fetoha ka mofuta o mong le o mong oa software ea Intel Quartus Prime. Phetoho ho:
- X e bontša phetoho e kholo ea IP. Haeba u nchafatsa software ea Intel Quartus Prime, u tlameha ho nchafatsa IP.
- Y e bonts'a IP e kenyelletsa likarolo tse ncha. Nchafatsa IP ea hau ho kenyelletsa likarolo tsena tse ncha.
- Z e bonts'a IP e kenyelletsa liphetoho tse nyane. Hlahisa IP ea hau bocha ho kenyelletsa liphetoho tsena.
Lintlha Tse Amanang
- Lintlha tsa Phatlalatso ea Phatlalatso ea Intel Quartus Prime Design Suite
- 25G Ethernet Intel Arria® 10 FPGA IP User Guide
- 25G Ethernet Intel Arria® 10 FPGA IP Design Example Bukana ea Mosebelisi
- Errata bakeng sa 25G Ethernet Intel FPGA IP Sebakeng sa Tsebo
3.1. 25G Ethernet Intel FPGA IP v19.4.1
Lethathamo la 9. v19.4.1 2020.12.14
| Intel Quartus Prime Version | Tlhaloso | Tšusumetso |
| 20.4 | Ntlafatso ea ho lekola bolelele ho liforeimi tsa VLAN: • Liphetolelong tse fetileng tsa 25G Ethernet Intel FPGA IP, phoso e feteletseng ea foreimi e boleloa ha maemo a latelang a finyelloa: 1. VLAN a. Ho fumanwa ha VLAN ho butswe. b. IP e fetisa/e amohela liforeimi tse bolelele bo fihlang ho bolelele ba foreimi ea TX/RX mmoho le 1 ho isa ho 4 octet. 2. SVLAN a. Ho fumanwa ha SVLAN ho butswe. b. IP e fetisa/e amohela liforeimi tse bolelele bo fihlang ho bolelele ba foreimi ea TX/RX mmoho le 1 ho isa ho 8 octet. • Besheneng ena, IP e nchafalitsoe ho lokisa boitšoaro bona. |
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| E ntlafalitse phihlello ea sebopeho sa 'mapa oa mohopolo oa Avalon ho boemo ba_* ho thibela nako ea ho qeta nako ea mohopolo oa Avalon nakong ea ho balloa liaterese tse sieo: • IP e ntjhafatswa hore e se be assert waitrequest ha aterese e seng teng e fumaneha boemong ba_* interface. |
3.2. 25G Ethernet Intel FPGA IP v19.4.0
Lethathamo la 10. v19.4.0 2019.12.16
| Intel Quartus Prime Version | Tlhaloso | Tšusumetso |
| 19.4 | rx_am_lock phetoho ea boitšoaro: • Liphetolelong tse fetileng tsa 25G Ethernet Intel FPGA IP, lets'oao la rx_am_lock le sebetsa ka mokhoa o ts'oanang le rx_block_lock ho mefuta eohle. • Phetolelong ena, bakeng sa mefuta e fapaneng ea RSFEC e lumelletsoeng ea IP, rx_am_lock joale e bolela ha ho notlelloa ha tokiso ho fihletsoe. Bakeng sa mefuta e sa lumelleng ea RSFEC, rx_am_lock e ntse e sebetsa ka mokhoa o ts'oanang le rx_block_lock. |
Letšoao la sehokelo, rx_am_lock, le sebetsa ka tsela e fapaneng le liphetolelo tse fetileng bakeng sa mefuta e lumelletsoeng ea RSFEC. |
| E ntlafalitse Qalo ea Pakete ea RX MAC: • Liphetolelong tse fetileng, RX MAC e sheba feela litlhaku tsa START ho tseba ho qala ha pakete. • Phetolelong ena, RX MAC joale e hlahloba lipakete tse kenang bakeng sa Start of Frame Delimiter (SFD), ho phaella ho START tlhaku ka ho feletseng. • Haeba selelekela sa "pass-through mode" se butswe, MAC e sheba feela hore na ho na le litlhaku tse QALANG ho lumella selelekela sa tloaelo. |
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| E kentse rejisetara e ncha ho thusa ho hlahloba selelekela: • Lirejiseteng tsa RX MAC, rejisetara e ho offset 0x50A [4] e ka ngolloa ho 1 ho nolofalletsa ho hlahloba selelekela. Rejisetara ena ke "ha o tsotelle" ha selelekela sa ho feta se buletsoe. |
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3.3. 25G Ethernet Intel FPGA IP v19.1
Lethathamo la 11. v19.1 Mmesa 2019
| Tlhaloso | Tšusumetso |
| E reha lebitso bocha paramethara ea Enable Altera Debug Master Endpoint (ADME) ho nolofalletsa Native PHY Debug Master Endpoint (NPDME) joalo ka ha Intel e fetolela bocha software ea Intel Quartus Prime Pro Edition. Software ea Intel Quartus Prime Standard Edition e ntse e sebelisa Enable Altera Debug Master Endpoint (ADME). | — |
3.4. 25G Ethernet IP Core v17.0
Lethathamo la 12. Version 17.0 May 2017
| Tlhaloso | Tšusumetso |
| Karolo ea moriti e kentsoeng bakeng sa lirekoto tsa lipalo-palo. • Lirejiseteng tsa lipalo tsa TX, ho tlositse rejisetara ea CLEAR_TX_STATS sebakeng sa offset 0x845 ka rejisetara e ncha ea CNTR_TX_CONFIG. Ngoliso e ncha e eketsa kopo ea moriti le phoso e hlakileng ea parity ho hanyane e hlakolang lirekoto tsohle tsa lipalo tsa TX. E kentse ngoliso e ncha ea CNTR_RX_STATUS ho offset 0x846, e kenyelletsang phoso ea parity le boemo ba kopo ea moriti. • Lirejiseteng tsa lipalo tsa RX, ho tlositsoe rejisetara ea CLEAR_RX_STATS sebakeng sa 0x945 ka registara e ncha ea CNTR_RX_CONFIG. Rejisetara e ncha e eketsa kopo ea moriti le phoso e hlakileng hanyane hanyane. seo se hlakola lirekoto tsohle tsa lipalo tsa TX. E kentse ngoliso e ncha ea CNTR_TX_STATUS ho offset 0x946, e kenyelletsang parity-error bit le boemo bo tlase bakeng sa kopo ea moriti. |
Karolo e ncha e ts'ehetsa ts'epahalo e ntlafalitsoeng ho lipalo tsa lipalo-palo. Ho bala lipalo-palo, qala ka ho beha palo ea kopo ea moriti bakeng sa sete eo ea lirejistara (RX kapa TX), ebe u bala ho tsoa ho sets'oants'o sa rejisetara. Litekanyetso tse baloang li emisa ho eketseha ha karolo ea moriti e ntse e sebetsa, empa likhakanyo tse ka tlase li ntse li eketseha. Ka mor'a hore u sete kopo bocha, li-counters li tsosolosa boleng ba tsona bo bokelitsoeng. Ho feta moo, likarolo tse ncha tsa ngoliso li kenyelletsa boemo ba parityerror le likarolo tse hlakileng. |
| Letshwao le fetotsweng la RS-FEC ho ikamahanya le Temana ya 108 e seng e phethetswe ya IEEE 802.3by tlhaloso. Nakong e fetileng karolo ea RS-FEC e ne e lumellana le 25G/50G Consortium Schedule 3, pele ho IEEE. ho phethela tlhaloso. |
Hona joale RX RS-FEC e lemoha le ho notlela li-marker tsa khale le tse ncha, empa TX RS-FEC e hlahisa feela sebopeho se secha sa IEEE sa alignment. |
Lintlha Tse Amanang
- 25G Ethernet IP Core User Guide
- Errata bakeng sa 25G Ethernet IP core ho Tsebo Base
3.5. 25G Ethernet IP Core v16.1
Lethathamo la 13. Version 16.1 October 2016
| Tlhaloso | Tšusumetso |
| Tokollo ea pele ho Intel FPGA IP Library. | — |
Lintlha Tse Amanang
- 25G Ethernet IP Core User Guide
- Errata bakeng sa 25G Ethernet IP core ho Tsebo Base
3.6. 25G Ethernet Intel Arria® 10 FPGA IP User Guide Archive
Liphetolelo tsa IP li tšoana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihla ho v19.1. Ho tsoa ho Intel Quartus Prime Design Suite software version 19.2 kapa hamorao, li-cores tsa IP li na le morero o mocha oa phetolelo ea IP.
Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.
| Intel Quartus Prime Version | IP Version | Bukana ea Mosebelisi |
| 20.3 | 19.4.0 | 25G Ethernet Intel Arria® 10 FPGA IP User Guide |
| 19.4 | 19.4.0 | 25G Ethernet Intel Arria 10 FPGA IP User Guide |
| 17.0 | 17.0 | 25G Ethernet Intel Arria 10 FPGA IP User Guide |
3.7. 25G Ethernet Intel Arria 10 FPGA IP Design Example User Tataiso ea Archives
Liphetolelo tsa IP li tšoana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihla ho v19.1. Ho tsoa ho Intel Quartus Prime Design Suite software version 19.2 kapa hamorao, li-cores tsa IP li na le morero o mocha oa phetolelo ea IP.
Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.
| Intel Quartus Prime Version | IP Core Version | Bukana ea Mosebelisi |
| 16.1 | 16.1 | 25G Ethernet Design Example Bukana ea Mosebelisi |
25G Ethernet Intel® FPGA IP Release Notes
Online Version
Romella Maikutlo
ID: 683067
Phetolelo: 2022.09.26
Litokomane / Lisebelisoa
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Intel 25G Ethernet Intel FPGA IP [pdf] Bukana ea Mosebelisi 25G Ethernet Intel FPGA IP, Ethernet Intel FPGA IP, Intel FPGA IP, FPGA IP, IP |